PEF20534

Serial Communication Controllers (SCCs)
• Four independent channels
• Full duplex data rates on each channel of up to 10 Mbit/s sync - 2 Mbit/s with DPLL, 2 Mbit/s async
• Full duplex data rate of up to 52 Mbit/s on any two channels in high speed mode (HDLC: Address Mode 0 and extended transparent protocol mode); up to 45 Mbit/s on any two channels in high speed mode (HDLC: PPP modes). The aggregate bandwith for all channels is limited to 108 Mbit/s per direction.
• 17 DWORDs deep receive FIFO per SCC (+ 128 DWORDs central receive FIFO).
• 8 DWORDs deep transmit FIFO per SCC (+ 128 DWORDs central transmit FIFO). Serial Interface
• On-chip clock generation or external clock sources
• On-chip DPLLs for clock recovery
• Baud rate generator
• Clock gating signals
• Clock gapping capability
• Programmable time-slot capability for connection to TDM interfaces (e.g. T1, E1)
• NRZ, NRZI, FM and Manchester data encoding
• Optional data flow control using modem control lines (RTS, CTS, CD)
• Support of bus configuration by collision detection and resolution
• HDLC/SDLC Protocol Modes
Automatic flag detection and transmission
Shared opening and closing flag
Generation of interframe-time fill '1's or flags
Detection of receive line status
Zero bit insertion and deletion
CRC generation and checking (CRC-CCITT or CRC-32)
Transparent CRC option per channel and/or per frame
Programmable Preamble (8 bit) with selectable repetition rate
Error detection (abort, long frame, CRC error, short frames)
• Bit Synchronous PPP Mode
Bit oriented transmission of HDLC frame (flag, data, CRC, flag)
Zero bit insertion/deletion
15 consecutive '1' bits abort sequence
• Octet Synchronous PPP Mode
Octet oriented transmission of HDLC frame (flag, data, CRC, flag)
Programmable character map of 32 hard-wired characters (00_H-1F_H)
Four programmable characters for additional mapping
Insertion/deletion of control-escape character (7D_H) for mapped characters
• Asynchronous PPP Mode
Character oriented transmission of HDLC frame (flag, data, CRC, flag)
Start/stop bit framing of single character
Programmable character map of 32 hard-wired characters (00_H-1F_H)
Four programmable characters for additional mapping
Insertion/deletion of control-escape character (7D_H) for mapped characters
• Asynchronous (ASYNC) Protocol Mode
Selectable character length (5 to 8 bits)
Even, odd, forced or no parity generation/checking
1 or 2 stop bits
Break detection/generation
In-band flow control by XON/XOFF
Immediate character insertion
Termination character detection for end of block identification
Time out detection
Error detection (parity error, framing error)
• BISYNC Protocol Mode
Programmable 6/8 bit SYN pattern (MONOSYNC)
Programmable 12/16 bit SYN pattern (BISYNC)
Selectable character length (5 to 8 bits)
Even, odd, forced or no parity generation/checking
Generation of interframe-time fill '1's or SYN characters
CRC generation (CRC-16 or CRC-CCITT)
Transparent CRC option per channel and/or per frame
Programmable Preamble (8 bit) with selectable repetition rate
Termination character detection for end of block identification
Error detection (parity error, framing error)
• Extended Transparent Mode
Fully bit transparent (no framing, no bit manipulation)
Octet-aligned transmission and reception
• Protocol and Mode Independent
Data bit inversion
Data overflow and underrun detection
Timer
Protocol Support
• Address Recognition Modes
No address recognition (Address Mode 0)
8-bit (high byte) address recognition (Address Mode 1)
8-bit (low byte) or 16-bit (high and low byte) address recognition (Non Auto Mode)
• HDLC Auto Mode
8-bit or 16-bit address generation/recognition
Support of LAPB/LAPD
Automatic handling of S- and I-frames
Automatic processing of control byte(s)
Modulo-8 or modulo-128 operation
Programmable time-out and retry conditions
SDLC Normal Response Mode (NRM) operation for slave
Microprocessor Interface
• 33 MHz/32-bit PCI bus interface option.
• 33 MHz/32-bit De-multiplexed bus interface option.
• 8-channel DMA controller with buffer chaining capability.
Master 15-word burst read and write capability (PCI Mode).
Master 4-word burst read and write capability (DEMUX Mode).
Slave single-word read and write capability.
• Circular interrupt queues with variable size.
• Maskable interrupts for each channel
Other Interfaces
• 8-/16-bit optional Local Bus Interface (LBI) for driving non-PCI peripherals in a PCI environment.
• Synchronous Serial Control interface (SSC) for controlling peripherals.
• 16-bit General Purpose Port (GPP).
General
• On chip Rx and Tx data buffer; the buffer size is 128 32-bit words each.
• Programmable buffer size in transmit direction per channel; buffer allocation in receive
direction on request.
• Programmable watermark for receive channels to control transfer of receive data to host memory.
• Two programmable watermarks for each transmit channel. One controlling data loading from host memory and one controlling transfer of transmit data to the corresponding Serial Communication Controller (SCC).
• Internal test loop capability.
• JTAG boundary scan test according to IEEE 1149.1
• Advanced low-power CMOS technology
• TTL-compatible inputs/outputs
3.3 V & 5 V power supply
3.3 V interfaces (TTL levels; 5 V tolerant in 5 V environment)
• P-FQFP-208-7 package
• The 10 MHz version only is available in extended temperature range -40 .. +85 °C (PEF 20534 H-10)