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Part Number: PH955L

 

 

 

D/C: 700

Description: Logic level N-channel enhancement mode Field Effect Transistor (FET) in a plastic package ...


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PH955L General Description


Logic level N-channel enhancement mode Field Effect Transistor (FET) in a plastic package using TrenchMOS™ technology.

PH955L Maximum Ratings

Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage (DC) 25 Tj 150 - 55 V
VDGR drain-gate voltage (DC) 25 Tj 150 ; RGS = 20 k - 55 V
VGS gate-source voltage   - ±20 V
ID drain current (DC) Tmb = 25 ; VGS = 5 V; Figure 2 and 3 - 62.5 A
Tmb = 100 ; VGS = 5 V; Figure 2 - 43.7 A
IDM peak drain current Tmb = 25 ; pulsed; tp 10 s; Figure 3 - 187 A
Ptot total power dissipation Tmb = 25 ; Figure 1 - 62.5 W
Tstg storage temperature   -55 +150
Tj junction temperature   -55 +150
Source-drain diode
IS source (diode forward) current (DC) Tmb = 25 - 52 A
ISM peak source (diode forward) current Tmb = 25 ; pulsed; tp 10 s - 156 A
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 44 A;
tp = 0.1 ms; VDD 55 V; RGS = 50 ;
VGS = 5 V; starting at Tj = 25
- 195 mJ
EDS(AL)R repetitive drain-source avalanche
energy
unclamped inductive load; ID = 44 A;
tp = 0.1 ms; VDD 55 V; RGS = 50 ;
VGS = 5 V; starting at Tj = 25
- 2 mJ

PH955L Features

·Logic level threshold
·Very low on-state resistance

PH955L Typical Application

·DC-to-DC converters
·General purpose power switching
·Motors, lamps and solenoids
·Portable appliances

PH955L Connection Diagram

PH955L  Connection Diagram

PH955L datasheet

PH955L
PDF/DataSheet Download

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