PI90LVT211

The PI90LV211 implements low voltage differential signaling (LVDS)to achieve clocking rates as high as 320 MHz with low skew. ThePI90LV211 is a low skew 1:6 fanout device designed explicitly for lowskew clock distribution applications. The device features a multiplexedclock input to allow for the distribution of a lower speed scanor test clock with the high-speed system clock. When LOW the SELpin will select the differential clock input.

Both a common enable and individual output enables are provided.When asserted the positive output will go LOW on the next negativetransition of the CLK (or SCLK) input. The enable function issynchronous so that the outputs will only be enabled/disabled whenthey are already in the LOW state. This avoids any chance ofgenerating a runt clock pulse when the device is enabled/disabledas can happen with an asynchronous control. The internal flip flopis clocked on the falling edge of the input clock, therefore allassociated specification limits are referenced to the negative edgef the clock input.

Individual synchronous enable controls and multiplexed clock inputsmake this device ideal as the first level distribution unit in adistribution tree. The individual enables could be used to allow for thedisabling of individual cards on a backplane in fault tolerant designs.