Features: • High performance Gigabit Fast Ethernet switch controller, wire-speed operation on every port.
• Single chip with twentyfour x 10/100 Mbit/s and two x Gbit/s Ports (10/100/1000 Mbit/s ports)
• SMII Interface on 10/100 Mbit/s ports supports auto-negotiation for speed and duplex setting.
• GMII and PMA Interface on Gigabit ports (full-duplex only) and optional MII interface support on Gigabit ports, Half duplex is supported in 10/100 Mbit/s mode only.
• Full-duplex IEEE 802.3x flow control and collision-based congestion control in half-duplex
• Provide packet switching functions between 1000/100/10 Mbit/s & fast Ethernet ports
• Support 802.3ad based port trunking for high-bandwidth inter-switch links.
• 2/4/8 10/100 Ports or 2 Gigabit ports can be combined to form trunks multiple trunks per device
ApplicationTypical PCI applications are add-on boards that require high-speed memory access,including LAN adapters, graphic adapters, hard drive controllers and SCSI cards. Using the PCI bus allows system designers to implement system critical components on a high bandwidth bus using low cost components so enhancing system price and performance.
There are three main types of devices that operate on the PCI bus:
• PCI Bus/System bridge: This Interfaces the PCI bus to the system processor and main memory. This device can act as a PCI master and arbitrate for systems that allow multiple bus masters,
• PCI bus add-on masters: Add-ons are devices that can operate the bus and may need access to other PCI add-ons or main memory on the system,
• PCI Bus Target-only add-ons: These are add-on devices that can only operate as targets. These devices respond to but do not initiate bus cycles.
The current implementation of the CPUIF supports only 33 MHz , 32-bit, target-only PCI Local Bus for 3.3 V operations.
Specifications
| Symbol |
Parameter |
MAXIMUM RATINGS |
Unit |
| min. |
max. |
| TA |
Ambient temperature under bias |
0 |
70 |
|
| Tstg |
Storage temperature |
-65 |
125 |
|
| VDD |
IC supply voltage |
-0.4 |
1.89 |
V |
| VDDP |
PAD (I/O) supply voltage |
-0.5 |
3.65 |
V |
| VS |
Voltage on any pin with respect to
ground |
-0.4 |
VDDP + 0.4 |
V |
| Imax |
Maximum current on all lines
connected to the backplane when
the DOC is without power supply;
at 5.5 V external signal level |
|
2.3 |
mA |
|
VESD,HBM |
ESD robustness1)
HBM: 1.5 kΩ, 100 pF |
2000 |
|
V |
Note: Stresses above those listed here may cause permanent damage to the device.Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1)According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993. The RF Pins 20, 21,26, 29, 32, 33, 34 and 35 are not protected against voltage stress > 300 V (versus VS or GND). The high frequency performance prohibits the use of adequate protective structures
DescriptionAs shown in the Functional Block diagram in Figure 10, the PLB 2224 consists of seven major blocks.
• 10 / 100 / 1000 Mbit/s Media Access Control MAC/GMAC,
• Receive FIFO / Rx. control (RX),
• Address Resolution Logic (ARL),
• Packet & Queue manager (PQC),
• TX (Transmit FIFO),
• CPU (cpu subsystem),
• Memory block (arbitration and storage).
PLB 2224 Data Sheet
