PLC42VA12

The new PLC42VA12 CMOS PLD from Philips Semiconductors exhibits a unique combination of the two architectural concepts that revolutionized the PLD marketplace.The PLC42VA12 Philips Semiconductors unique Output Macro Cell (OMC) embodies all the advantages and none of the disadvantages associated with the "V" type Output Macro Cell devices. This new design, combined with added functionality of two programmable arrays, represents a significant advancement in the configurability and efficiency of multi-function PLDs.

Features of the PLC42VA12 are:(1)registered output with feedback; (2)registered input; (3)combinatorial I/O with buried register; (4)dedicated I/O with feedback; (5)dedicated input (combinatorial); (6)reprogrammable100% tested for programmability; (7)eleven clock sources; (8)register preload and diagnostic test mode features; (9)security fuse; (10)bypassed registers are 100% functional with separate input and feedback paths; (11)individual output enable control functions.The output of each buried register can also be configured as inverting or non-inverting via the input buffer which feeds back to the AND array.

The absolute maximum ratings of the PLC42VA12 can be summarized as:(1)supply voltage:-0.5 to 7 V;(2)storage temperature range:-65 to 150;(3)input voltage:-0.5 to Vcc+0.5V;(4)output voltage:-0.5 to Vcc+0.5V;(5)operating temperature:0 to 75;(6)input currents:-10 to 10mA;(7)output currents:24mA.Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.The most significant Output Macro Cell(OMC) feature is the implementation of the register bypass function. Any of the 10 J-K/D registers can be individually bypassed, thus creating a combinatorial I/O path from the AND array to the output pin. Unlike other Output Macro Cell-type devices, the register in the OMC is fully functional as a buried register. Furthermore, both the combinatorial I/O and the buried register have separate input paths (from the AND array) and separate feedback paths (to the AND array).This feature provides the capability to operate the buried register independently from the combinatorial I/O.