PM5313

1.1 General
• Monolithic SONET/SDH PAYLOAD EXTRACTOR/ALIGNER for use in STS-12 (STM-4/AU3 or STM-4/AU4) or STS-12c (STM-4-4c) interface applications, operating at serial interface speeds of up to 622.08 Mbit/s.
• Provides integrated clock and data recovery and clock synthesis for direct connection to optical modules.
• Supports a duplex byte-serial 77.76 Mbyte/s STS-12 (STM-4/AU3 or STM-4/AU4) or STS-12c (STM-4-4c) line side interface for use in applications where by-passing clock recovery, clock synthesis, and serializer-deserializer functionality is desired.
• Supports clock recovery bypass for use in applications where external clock recovery is desired.
• Complies with Bellcore GR-253-CORE jitter tolerance (1995 issue), jitter transfer and intrinsic jitter criteria.
• Provides control circuitry to comply with Bellcore GR-253-CORE WAN clocking requirements related to wander transfer, holdover and long term stability when using an external VCXO.
• Provides termination for SONET Section and Line, SDH Regenerator Section and Multiplexer Section transport overhead, and path overhead of twelve STS-1 (STM-0/AU3) paths, four STS-3/3c (STM-1/AU3/AU4) paths or a single STS-12c (STM-4-4c) path.
• De-multiplexes an STM-4 receive stream to four STM-1 Telecom DROP bus streams.
• Multiplexes four STM-1 Telecom ADD bus streams to an STM-4 transmit stream.
• Maps twelve STS-1 (STM-0/AU3) payloads, four STS-3/3c (STM-1/AU3/AU4) payloads or a single STS-12c (STM-4-4c) payload to system timing reference, accommodating plesiochronous timing offsets between the references through pointer processing.
• Maps twelve DS3 bit streams into an STS-12 (STM-4/AU3) frame.
• Provides Time Slot Interchange (TSI) function at the Telecom ADD and DROP buses for grooming twelve STS-1 (STM-0/AU3) paths or four STS-3/3c (STM-1/AU3/AU4) paths.
• Supports line loopback from the line side receive stream to the transmit stream and diagnostic loopback from a Telecom ADD bus interface to a Telecom DROP bus interface.
• Supports OC-48(STM-16) applications by providing parallel receive and transmit line side ports used to connect to front-end OC-48 devices.
• Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
• Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
• Low power 3.3V CMOS with TTL compatible digital inputs and CMOS/TTL digital outputs. PECL inputs and outputs are 3.3V and 5V compatible.
• Industrial temperature range (-40°C to +85°C).
• 520 pin Super BGA package.
1.2 SONET Section and Line / SDH Regenerator and Multiplexer Section
• Frames to the STS-12 (STM-4) receive stream and inserts the framing bytes (A1, A2) and the STS identification byte (J0) into the transmit stream; descrambles the received stream and scrambles the transmit stream.
• Calculates and compares the bit interleaved parity (BIP) error detection codes (B1, B2) for the receive stream. Calculates and inserts B1 and B2 in the transmit stream. Accumulates near end errors (B1, B2) and far end errors
 M1) and inserts line remote error indications (REI) into the Z2 (M1) growth byte based on received B2 errors.
• Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms based on received B2 errors.
• Extracts and serializes the order wire channels (E1, E2), the data communication channels (D1-D3, D4-D12) and the section user channel (F1) from the received stream, and inserts the corresponding signals into the transmit stream.
• Extracts and serializes the automatic protection switch (APS) channel (K1, K2) bytes, filtering and extracting them into internal registers for the receive stream. Inserts the APS channel into the transmit stream.
• Extracts and filters the synchronization status message (Z1/S1) byte into an internal register for the receive stream. Inserts the synchronization status message (Z1/S1) byte into the transmit stream.
• Extracts a 64 byte or 16 byte section trace (J0) message using an internal register bank for the receive stream. Detects an unstable section trace message or mismatch with an expected message, and optionally inserts Line and Path AIS on the system DROP side upon either of these conditions. Inserts a 64 byte or 16 byte section trace (J0) message using an internal register bank for the transmit stream. Provides access to the accepted message via the microprocessor port.
• Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line remote defect indication (RDI), line alarm indication signal (AIS), and protection switching byte failure alarms on the receive stream. Optionally returns line RDI in the transmit stream.
• Provides a transmit and receive ring control port, allowing alarm and maintenance signal control and status to be passed between mate SPECTRA-622s for ring-based add drop multiplexer and line multiplexer applications.
• Configurable to force Line AIS in the transmit stream.
1.3 SONET Path / SDH High Order Path
• Accepts a multiplex of twelve STS-1 (STM-0/AU3) streams, four STS-3/3c (STM-1/AU3/AU4) streams or a single STS-12c (STM-4-4c) stream, interprets the STS (AU) pointer bytes (H1, H2, and H3), extracts the synchronous payload envelope(s) and processes the path overhead for the receive stream.
• Constructs a byte serial multiplex of twelve STS-1 (STM-0/AU3) streams or four STS-3/3c (STM-1/AU3/AU4) stream on the transmit side.
• Detects loss of pointer (LOP), loss of tributary multiframe (LOM), path alarm indication signal (PAIS) and path (auxiliary and enhanced) remote defect indication (RDI) for the receive stream. Optionally inserts path alarm indication signal (PAIS) and path remote defect indication (RDI) in the transmit stream.
• Extracts and serializes the entire path overhead from the twelve STS-1 (STM-0/AU3), four STS-3/3c (STM-1/AU3/AU4) or the single STS-12c (STM-4-4c) receive streams. Inserts the path overhead bytes in the twelve STS-1 (STM-0/AU3), four STS-3/3c (STM-1/AU3/AU4) or single STS-12c (STM-4-4c) stream for the transmit stream. The path overhead bytes may be sourced from internal registers or from bit serial path overhead input stream. Path overhead insertion may also be disabled.
• Extracts the received path signal label (C2) byte into an internal register and detects for path signal label unstable and for signal label mismatch with the expected signal label that is downloaded by the microprocessor. Inserts the path signal label (C2) byte from an internal register for the transmit stream.
• Extracts a 64 byte or 16 byte path trace (J1) message using an internal register bank for the receive stream. Detects an unstable path trace message or mismatch with an expected message, and inserts Path RAI upon either of these conditions. Inserts a 64 byte or 16 byte path trace (J1) message using an internal register bank for the transmit stream. Provides access to the accepted message via the microprocessor port.
• Detects received path BIP-8 and counts received path BIP-8 errors for performance monitoring purposes. BIP-8 errors are selectable to be treated on a bit basis or block basis. Optionally calculates and inserts path BIP-8 error detection codes for the transmit stream.
• Counts received path remote error indications (REIs) for performance monitoring purposes. Optionally inserts the path REI count into the path status byte (G1) basis on bit or block BIP-8 errors detected in the receive path. Reporting of BIP-8 errors is on a bit or block bases independent of the accumulation of BIP-8 errors.
• Maintains the existing tributary multiframe sequence on the H4 byte until a new phase alignment has been verified.
• Provides a serial alarm port communication of path REI and path RDI alarms to the transmit stream of a mate SPECTRA-622 in the returning direction.
1.4 System Side Interfaces
• Supports Telecombus interfaces by indicating/accepting the location of the STS identification byte (C1), optionally the path trace byte(s) (J1), optionally the first tributary overhead byte(s) (V1), and all synchronous payload envelope bytes in the byte serial stream.
• Configurable to support four 19.44 MHz byte Telecombus interfaces or a single 77.76 MHz byte Telecombus interface.
• For Telecombus interface, accommodates phase and frequency differences between the receive/transmit streams and the DROP/ADD busses via pointer adjustments.
• Supports bit serial DS3 interfaces for mapping into and out of the 12 possible STS-1 SPE's in an STS-12 (STM-4/AU3).
• For the DS3 interface, provides optional insertion of DS3 AIS in both the ADD and DROP directions.
• Configurable to support a mix of traffic from the DS-3 interface and the Telecombus interface selectable on an STS-1 basis.
• Provides TSI function to interchange or groom twelve STS-1 (STM-0/AU3) paths or four STS-3/3c (STM-1/AU3/AU4) paths at the Telecom ADD and DROP buses. For STS-3 (STM-1/AU3) paths, grooming can be performed at the STS-1 (STM-0/AU3) level.

The PM5313 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER (SPECTRA-622) terminates the transport and path overhead of STS-12 (STM-4/AU3 or STM- 4/AU4) and STS-12c (STM-4-4c) streams at 622.08 Mbit/s. The SPECTRA-622 implements significant functions for a SONET/SDH compliant line interface, as well as DS3 mapping.

The SPECTRA-622 receives SONET/SDH frames via a bit serial interface, recovers clock and data, and terminates the SONET/SDH section (regenerator section), line (multiplexer section), and path. SPECTRA-622 performs framing (A1, A2), descrambling, detects alarm conditions, and monitors section and line bit interleaved parity (BIP) (B1, B2), accumulating error counts at each level for performance monitoring purposes. B2 errors are also monitored to detect signal fail and signal degrade threshold crossing alarms. Line remote error indications (M1) are also accumulated. A 16 or 64 byte section trace (J0) message may be buffered and compared against an expected message. In addition, the SPECTRA-622 interprets the received payload pointers (H1, H2), detects path alarm conditions, detects and accumulates path BIPs (B3), monitors and accumulates path Remote Error Indications (REIs), accumulates and compares the 16 or 64 byte path trace (J1) message against an expected result and extracts the synchronous payload envelope (virtual container). All transport and path overhead bytes are extracted and serialized on lower rate interfaces, allowing additional external processing of overhead, if desired.

The extracted SPE (VC) is placed on a Telecom DROP bus and optionally serialized into DS3 streams. For Telecombus applications, frequency offsets (e.g., due to plesiochronous network boundaries, or the loss of a primary reference timing source) and phase differences (due to normal network operation) between the received data stream and the DROP bus are accommodated by pointer adjustments in the DROP bus. For the DS3 application, the SPECTRA-622 demaps the DS3s from the STS-12 (STM-4/AU3/AU4) SPE and provides serialized bit streams with derived clocks. Both the Telecom and DS3 DROP buses can be active at the same time supporting a mixed use de-multiplexer function on the system DROP side.

The SPECTRA-622 transmits SONET/SDH frames, via a bit serial interface, and formats section (regenerator section), line (multiplexer section), and path overhead appropriately. The SPECTRA-622 provides transmit path origination for a SONET/SDH STS-12 (STM-4/AU3 or STM-4/AU4) or STS-12c (STM-4-4c) stream. SPECTRA-622 performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section and line BIPs (B1, B2) as required to allow performance monitoring at the far end. Line remote error indications (M1) are optionally inserted. A 16 or 64 byte section trace (J0) message may be inserted.

In addition, the SPECTRA-622 generates the transmit payload pointers (H1, H2), creates and inserts the path BIP, optionally inserts a 16 or 64 byte path trace (J1) message, optionally inserts the path status byte (G1). In addition to its basic processing of the transmit SONET/SDH overhead, the SPECTRA-622 provides convenient access to all overhead bytes, which are inserted serially on lower rate interfaces, allowing additional external sourcing of overhead, if desired. The SPECTRA-622 also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors and BIP errors, which are useful for system diagnostics and tester applications.

The inserted SPE (VC) is either sourced from a Telecombus ADD stream or from DS3 serial streams. For Telecombus applications, the SPECTRA-622 maps the SPE from a Telecom ADD bus into the transmit stream. Frequency offsets (e.g.,due to plesiochronous network boundaries, or the loss of a primary reference timing source) and phase differences (due to normal network operation) between the transmit data stream and the ADD bus are accommodated by pointer adjustments in the transmit stream. For the DS3 application, the SPECTRA-622 maps the DS3s into an STS-12 (STM-4/AU3/AU4) SPE. Both the Telecom and DS3 ADD buses can be active at the same time supporting a mixed use multiplexer function on the system ADD side.

The SPECTRA-622 supports Time-Slot Interchange (TSI) on the Telecom ADD and DROP buses. On the DROP side, the TSI views the receive stream as twelve independent time-division multiplexed columns of data (i.e. twelve constituent STS-1 (STM-0/AU3) or equivalent streams or time-slots or columns).

Any column can be connected to any time-slot on the DROP bus. Both column swapping and broadcast are supported. Time-Slot Interchange is independent of the underlying payload mapping formats. Similarly, on the ADD side, data from the ADD bus is treated as twelve independent time-division multiplexed columns. Assignment of data columns to transmit time-slots (STS-1 (STM-0/AU3) or equivalent streams) is arbitrary.

The transmitter and receiver are independently configurable to allow for asymmetric interfaces. Ring control ports are provide to pass control and status information between mate transceivers. The SPECTRA-622 is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. The SPECTRA-622 is implemented in low power, +3.3 Volt, CMOS technology. It has TTL and pseudo ECL (PECL) compatible inputs and outputs and is packaged in a 520 pin SBGA package.