PM7380-PI

The PM7380-PI is a kind of Single-chip multi-channel HDLC controller. It is available in 329 Plastic Ball Grid Array (PBGA) package.The typical applications include (1)IETF PPP interfaces for routers; (2)TDM switches; (3)Frame Relay interfaces for ATM or Frame Relay switches and multiplexors; (4)FUNI or Frame Relay service inter-working interfaces for ATM switches and multiplexors; (5)Internet/Intranet access equipment; (6)Packet-based DSLAM.

There are some features of PM7380-PI as follows: (1)Supports up to 672 bi-directional HDLC channels assigned to a maximum of 32 H-MVIP digital telephony buses at 2.048 Mbps per link. The links are grouped into 4 logical groups of 8 links. A common clock and a type 0 framepulse is shared among  links in each logical group. The number of time-slots assigned to an HDLC channel is programmable from 1 to 32; (2)Supports up to 672 bi-directional HDLC channels assigned to a maximum of 8 H-MVIP digital telephony buses at 8.192 Mbps per link. The links share a common clock and a type 0 frame pulse. The number of time-slots assigned to an HDLC channel is programmable from 1 to 128; (3)Supports up to 672 bi-directional HDLC channels assigned to a maximum of 32 channelised T1/J1 or E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for E1); (4)Supports up to 32 bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link, subject to a maximum aggregate link clock rate of 64 MHz in each direction. Channels assigned to links 0 to 2 support a clock rate of up to 51.84 MHz. Channels assigned to links 3 to 31 support aclock rate of up to 10 MHz; (5)Supports three bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link of up to 51.84 MHz when SYSCLK is running at 45 MHz; (6)Supports a mix of up to 32 channelised, unchannelised and H-MVIP links, subject to the constraint of a maximum of 672 channels and a maximum aggregate link clock rate of 64 MHz in each direction.; (7)Links configured for channelised T1/J1/E1 or unchannelised operation support the gapped-clock method for determining time-slots which is backwards compatible with the FREEDM-8 and FREEDM-32 devices; (8)Supports two levels of non-preemptive packet priority on each transmit channel. Low priority packets will not begin transmission until all high priority packets are transmitted.; (9)Alternatively, for each channel, the transmitter supports a transparent mode where each octet is inserted transparently from host memory. For channelised links, the octets are aligned with the transmit time-slots.

Then is about the absolute maximum ratings of PM7380-PI: (1)Case Temperature under Bias: -40 to +85; (2)Storage Temperature: -40 to +125; (3)Supply Voltage (+3.3 Volt VDD3.3): -0.3V to +4.6V; (4)Supply Voltage (+2.5 Volt VDD2.5): -0.3V to +3.5V; (5)Voltage on Any non-PCI Pin:  -0.3V to +6.0V; (6)Voltage on Any PCI Pin:  -0.5V to VDD3.3 + 0.5V; (7)Static Discharge Voltage:  ±1000 V; (8)Latch-Up Current:  ±100 mA; (9)DC Input Current:  ±20 mA; (10)Lead Temperature:  +230°C; (11)Absolute Maximum Junction Temperature: +150.