PM9311-UC

The ETT1/TT1 switch fabric uses a refresh mechanism to restore Scheduler state after a fault has occurred or a new board has been added to a dual-Scheduler ETT1/TT1 system. The refresh process is initiated by the ETT1/TT1 CPU. The CPU sends a Refresh command to all ETT1/TT1 ports that need to have their Scheduler state refreshed.

The refresh process has two main phases:
1. Send data from EPP/PP to Scheduler.
2. The CPU writes to the Go Scheduler register in the EPP/PP, which has the effect of synchronizing the two Schedulers and restarting the arbitration of non-TDM traffic.

The defect occurs at phase 2. The Go-Schedulers command may sometimes cause some of the Scheduler AIB links to turn themselves off for up to 4 cell times, after which they turn back on. This may cause data loss, and will certainly cause unwanted interrupts.

What happens is that, internally to the Scheduler, the AIB logic associated with a given port can mis-read its configuration state and will use the configuration state of a different port. So, for example, the AIB for port 8 (inside the Scheduler) may temporarily adopt the configuration of the AIB for port 0. If port 0 is not connected, then its AIB is turned off, and so port 8 will turn off its own AIB. The port will restore its correct configuration within four cell times (160ns), but that is too late to prevent the problem.

The deficiency is in the Scheduler logic that manages the state information for each port and AIB, and has been demonstrated in our simulations of the system and on real TT1 and ETT1 systems.