PSD4135G2

Features:

`5 V±10% Single Supply Voltage:
`Up to 4 Mbit of Primary Flash Memory (8 uniform sectors)
` 256Kbit Secondary Flash Memory (4 uniform sectors)
` Up to 64 Kbit SRAM
` Over 3,000 Gates of PLD: DPLD and CPLD
` 52 Reconfigurable I/O ports
` Enhanced JTAG Serial Port
` Programmable power management
` High Endurance:
100,000 Erase/Write Cycles of Flash Memory
1,000 Erase/Write Cycles of PLD


Application

• 4 Mbit of Flash memory
• A secondary Flash memory for boot or data
• Over 3,000 gates of Flash programmable logic
• 64 Kbit SRAM
• Reconfigurable I/O ports
• Programmable power management.


Specifications

Symbol	Parameter	Condition	Min.	Max.	Unit
TSTG	Storage Temperature	PLDCC	65	+ 125	°C
	Operating Temperature	Commercial	0	+ 70	°C
		Industrial	40	+ 85	V
	Voltage on any Pin	With Respect to GND	0.6	+ 7	V
VPP	Device Programmer Supply Voltage	With Respect to GND	0.6	+ 14	V
VCC	Supply Voltage	With Respect to GND	0.6	+ 7	V
	ESD Protection		>2000		V

Description

The JTAG configuration bit (non-volatile) inside the PS9821-1 can be set by the user in the PSDsoft. Once this bit is set and programmed in the PSD, the JTAG pins are dedicated to JTAG at all times and is in compliance with IEEE 1149.1. After power up the standard JTAG signals (TDI, TDO TCK and TMS) are inputs, waiting for a serial command from an external JTAG controller device (such as FlashLink or Automated Test Equipment). When the enabling command is received from the external JTAG controller, TDO becomes an output and the JTAG channel is fully functional inside the PSD. The same command that enables the JTAG channel may optionally enable the two additional JTAG pins, TSTAT and TERR.

The PS9821-1 supports JTAG ISP commands, but not Boundary Scan. ST's PSDsoft software tool and FlashLink JTAG programming cable implement these JTAG-ISP commands.