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Description: The PSD8XXFX family of memory systems for mi-crocontrollers (MCUs) brings In-System-Program- mability ...


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PSD813F2/3/4/5, General Description


The PSD8XXFX family of memory systems for mi-crocontrollers (MCUs) brings In-System-Program- mability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD8XXFX devices combine many of the peripheral functions found in MCU based applications.

Table 1 summarizes all the devices in the PSD834F2, PSD853F2, PSD854F2.

The CPLD in the PSD8XXFX devices features an optimized macrocell logic architecture. The PSD macrocell was created to address the unique re-quirements of embedded system designs. It al- lows direct connection between the system address/data bus, and the internal PSD8XXFX registers, to simplify communication between the MCU and other supporting devices.

The PSD8XXFX device includes a JTAG Serial Programming interface, to allow In-System Pro- gramming (ISP) of the entire device. This feature reduces development time, simplifies the manu-facturing flow, and dramatically lowers the cost of field upgrades. Using ST's special Fast-JTAG pro-gramming, a design can be rapidly programmed into the PSD8XXFX in as little as seven seconds.

The innovative PSD8XXFX family solves key problems faced by designers when managing dis-crete Flash memory devices, such as:
First-time In-System Programming (ISP)
Complex address decoding
Simultaneous read and write to the device.

The JTAG Serial Interface block allows In-System Programming (ISP), and eliminates the need for an external Boot EPROM, or an external program-mer. To simplify Flash memory updates, program execution is performed from a secondary Flash memory while the primary Flash memory is being updated. This solution avoids the complicated hardware and software overhead necessary to im-plement IAP.

ST makes available a software development tool,PSDsoft Express, that generates ANSI-C compli-ant code for use with your target MCU. This code allows you to manipulate the non-volatile memory (NVM) within the PSD8XXFX. Code examples are also provided for:
Flash memory IAP via the UART of the host MCU
Memory paging to execute code across several PSD8XXFX memory pages
Loading, reading, and manipulation of PSD8XXFX macrocells by the MCU.

PSD813F2/3/4/5, Maximum Ratings

Symbol Parameter Min. Value Unit
TSTG Storage Temperature 65 125
TLEAD Lead Temperature during Soldering (20 seconds max.) 1
235

VIO Input and Output Voltage (Q = VOH or Hi-Z) 0.6 7.0 V
VCC Supply Voltage
0.6 7.0 V
VPP Device Programmer Supply Voltage
-0.6 14.0 V
VESD Electrostatic Discharge Voltage (Human Body model) 2 2000 2000 V
Note: 1. IPC/JEDEC J-STD-020A
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

PSD813F2/3/4/5, Features

` 5V±10% Single Supply Voltage
` Up to 2Mbit of Primary Flash Memory (8 uniform sectors, 32K x 8)
` Up to 256Kbit Secondary Flash Memory (4 uniform sectors)
` Up to 256Kbit SRAM
` Over 3,000 Gates of PLD: DPLD and CPLD
` 27 Reconfigurable I/O ports
` Enhanced JTAG Serial Port
` Programmable power management
` High Endurance:
100,000 Erase/WRITE Cycles of Flash Memory
1,000 Erase/WRITE Cycles of PLD

PSD813F2/3/4/5, datasheet

PSD03
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