PSD853F2-70J

The feature of PSD853F2-70J are as follows: (1)flash in-system programmable (isp) peripheral for 8-bit mcus; (2)dual bank flash memories; (3)up to 256 kbit battery-backed sram; (4)27 reconfigurable i/o ports; (5)enhanced jtag serial port; (6)pld with macrocells; (7)27 individually configurable i/o port pins; (8)in-system programming (isp) with jtag; (9)page register; (10)programmable power management.

The following is about the electrical characteristics of PSD853F2-70J: (1)Input High Voltage: 2V min and VCC+0.5V max at 4.5 V < VCC < 5.5 V; (2)Input Low Voltage: -0.5V min and 0.8V max at 4.5 V < VCC < 5.5 V; (3)Reset High Level Input Voltage: 0.8VCC min and VCC+0.5V max; (4)Reset Low Level Input Voltage: -0.5V min and 0.2VCC-0.1V max; (5)Reset Pin Hysteresis: 0.3V; (6)Output Low Voltage: 0.1V max at IOL = 20A, VCC = 4.5 V; (7)SRAM Stand-by Voltage: 2.0V min and VCC max; (8)Input Leakage Current: -1A min and 1A max at VSS < VIN < VCC; (9)Output Leakage Current: -10A min and 10A max at 0.45 < VOUT < VCC.