Q0256

Forward Error Correction (FEC)techniques provide higher throughput data rates with improved bit error rate performance for power-limited (and in some cases bandwidth-limited) digital communication channels. Convolutional encoding of data combined with Viterbi decoding at the receiving node is the industry PEC standard for digital channels, especially those concerned with errors caused by the introduction of additive white gaussian noise. Satellite communication channels are examples of this noise environment. Figure 1 shows a typical application of PEC techniques in a communication system.

The Q0256 decoder has been specifically designed for low data rate, high volume applications. It is well suited for many commercial satellite communication networks, including INMARSAT and INTELSAT. The low cost and high performance of the Q0256 device also make it ideal for PEC requirements in systems such as DBS, VSAT, digital modems and digital cellular telephone applications. The Q0256 device provides convolutional encoding and Viterbi decoding of data channels and offers powerful built-in features. The capabilities of this single-chip device have been optimized for modern digital communication channels up to 800 Kbps. Figures 2 and 8 show block diagrams of the encoder and decoder functions of the Q0256 FEC system. The decoder processes data at one of four selectable code rates(1/3, 1/2, 3/4, and 7/8)using industry standard constraint length seven algorithms, and can operate at other code rates with a minimum of external circuitry. It offers built-in synchronization capability for standard BPSK {Binary Phase Shift Keying}, QPSK {Quadrature}, and OQPSK {Offset Quadrature} modems and operates with either 1 bit hard-decision data or 3-bit soft-decision encoded data.

The features for Q0256 are full custom device for low cost, high volume applications; stand-alone pull-duplex rate 1/3, 1/2,3/4, and 7/8 encoder/decoder; two pin-for-pin compatible versions: 256 and 800 kbps maximum data rates; on-chip bit error rate monitor; processor interface simplifies control and status; 3-bit soft-decision decoder inputs; 5.2 dB coding gain (rate1/2) 5.5 dB coding gain (rate1/3) at 105 BER; easy implementation of additional code rates; automatic synchronization capability; parallel or serial decoder data inputs; on-chip V.35 data scrambler/descrambler; low power CMOS implementation; standard 84-pin LCC package; complies with INMARSAT standard-b, and INTELSAT IESS-309.