QL2003

Features: ·Total of 118 I/O Pins - 110 bidirectional input/output pins, PCI-compliant at 5.0V in -1/-2 speed grades -4 high-drive input-only pins - 4 high-drive input/distributed network pins·Four Low-Skew (less than 0.5ns) Distributed Networks - Two array networks available to logic cell flip-flo...

product image

QL2003 Picture
SeekIC No. : 004468108 Detail

QL2003: Features: ·Total of 118 I/O Pins - 110 bidirectional input/output pins, PCI-compliant at 5.0V in -1/-2 speed grades -4 high-drive input-only pins - 4 high-drive input/distributed network pins·Four L...

floor Price/Ceiling Price

Part Number:
QL2003
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/4/26

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

·Total of 118 I/O Pins
   - 110 bidirectional input/output pins, PCI-compliant at 5.0V in -1/-2 speed grades
   - 4 high-drive input-only pins
   - 4 high-drive input/distributed network pins 
·Four Low-Skew (less than 0.5ns) Distributed Networks
   - Two array networks available to logic cell flip-flop clock, set, and reset - each driven by an input-only pin
   - Two global clock/control networks available to F1 logic input, and logic cell flip-flop clock, set, reset; input and I/O register clock, reset, enable; and output enable controls - each driven by an input-only pin, or any input or I/O pin, or any logic cell output or I/O cell feedback
·High Performance
   - Input + logic cell + output delays under 6 ns
   - Datapath speeds exceeding 225 MHz
   - Counter speeds over 200 MHz



Pinout

  Connection Diagram


Specifications

Supply Voltage .......... -0.5 to 7.0V
Input Voltage ...... -0.5 to VCC +0.5V
 ESD Pad Protection ....... ±2000V
DC Input Current ......... ±20 mA
Latch-up Immunity ....... ±200 mA
Storage Temperature....-65 to + 150
Lead Temperature ..........300




Description

The QL2003 is a 3,000 usable ASIC gate, 5,000 usable PLD gate member of the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination of architecture, technology, and software tools to provide high speed, high usable density, low price, and flexibility in the same devices. The flexibility and speed make pASIC 2 devices an efficient and high performance silicon solution for designs described using HDLs such as Verilog and VHDL, as well as schematics.

The QL2003 contains 192 logic cells. With 118 maximum I/Os, the QL2003 is available in 84-PLCC, 100-pin TQFP and 144-pin TQFP packages.

Software support for the complete pASIC families, including the QL2003, is available through three basic packages. The turnkey QuickWorks® package provides the most complete FPGA software solution from design entry to logic synthesis (by Synplicity, Inc.), to place and route, to simulation. The QuickToolsTM and QuickChipTM packages provide a solution for designers who use Cadence, Mentor, Synopsys, Viewlogic, Veribest, or other thirdparty tools for design entry, synthesis, or simulation.




Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
Potentiometers, Variable Resistors
Audio Products
Circuit Protection
View more