Features: Advanced PCI Features
• DMA Chaining mode for queued DMA transactions
• Four-channel DMA mastering, plus a SPCI (Single PCI Access) mode
• Unlimited bursts supported in Master and Target mode
• Two Master Write FIFOs and two Master Read FIFOs, each 64-deep and 64 bits wide
• Target Read and Write FIFOs for pre-fetched reads and multipleposted writes
• Programmable interrupt controller
• I2O compliant under microprocessor control
• 16 Mailbox registers for message passing and semaphores
• Extended configuration space allowing Messaged Interrupts, power management, and future PCI enhancement support
Advanced Master DMA Features
• Programmable DMA Channel Arbitration Scheme
• SPCI (Single PCI Access) mode may initiate any PCI Master command
• DMA controller configurable via PCI or back-end
• DMA Chaining mode allows a linked list of DMA transfers to occur without user interventionApplicationThe QL5064 device supports maximum PCI transfer rates, so many applications exist which are ideally suited to the device's high performance. High speed data communications, telecommunications, and computing systems are just a few of the broad range of applications areas that can benefit from the high speed PCI interface and programmable logic.
The PCI Interface can also act as a PCI Host Controller. This can be accomplished by glue-less interface to most popular 8/16/32/64-bit microprocessors.
Specifications
|
VCC Voltage |
-0.5 to 4.6V |
DC Input Current |
±20 mA |
|
VCCIO Voltage |
-0.5 to7.0V
|
ESD Pad Protection |
±2000V |
|
Input Voltage |
-0.5V to VCCIO +0.5V |
Storage Temperature |
-65 to +150 |
|
Latch-up Immunity |
±200 mA |
Maximum Lead Temperature |
300 |
DescriptionThe QL5064 device in the QuickLogic QuickPCI ESP (Embedded Standard Products) family provides a complete and customizable PCI interface solution combined with 74,000 system gates of programmable logic. This device eliminates any need for the designer to worry about PCI bus compliance, yet allows for the maximum possible PCI bus bandwidth.
The programmable logic portion of the QL5064 is built from 792 QuickLogic Logic Cells, and 11 QuickLogic Dual-Port RAM Blocks. The configurable RAM blocks can each operate in 64x18, 128x9, 256x4, or 512x2 mode. These dual-port RAM blocks can be cascaded to achieve deeper or wider configurations. QL5064 can also be combined with logic cells to form FIFOs. See the RAM section of this data sheet for more information.
The QL5064 device includes a complete pre-designed PCI Initiator/Target interface offering full burst mode transfers at 32 or 64 bits per clock cycle. At 66 MHz, this device offers support for 533 Mbytes/sec data transfer rates (66.6 MHz * 8 bytes per transfer). At the maximum speed of 75 MHz (exceeding the current maximum speed specification for PCI), the QL5064 device can achieve 600 Mbytes/sec data transfer rates. The PCI interface is configured via internal programmable configuration bits, so no external EEPROM or memory is needed.
The QL5064 device meets PCI 2.2 electrical and timing specifications and has been fully hardwaretested.This device also supports the Win'98 and PC'98 standards. The QL5064 device features 3.3- volt operation with multi-volt compatible I/Os. Thus it can easily operate in 3.3-volt only systems, as well as mixed 3.3 volt/5 volt system. It can be placed on a universal signaling PCI board.
A wide range of additional features complements the QL5064 device. The FPGA side of the device is 5 volt and 3.3-volt PCI-compliant and is capable of implementing FIFOs at 160 MHz, and counters at over 250 MHz. I/O pins provide individually controlled output enables, dedicated input/feedback registers, and full JTAG capability for boundary scan and test. In addition, the QL5064 device provides the benefits of non-volatility, high design security, immediate functionality on power-up, and a selfcontained single chip solution.
QL5064 Data Sheet
