RD_DATA

RD_DATA conforms to the appropriate standard(s). In general, standards do not define the internal user interface, only the external interfaces and protocols.

Therefore, Avnet Memec has created a simple FIFO interface to this core for easy user connectivity. RD_DATA describes this Avnet Memec created interface. Please consult the appropriate standards document for all external signaling.

TOP_SLAVE

This is the top level of the core. RD_DATA's only purpose is to serve as a container to instantiate the transmit & receive modules. TOP_SLAVE is also where the generics are located that configure the core. These parameters are then passed down to the TX & RX modules.

TOP_EGR_SLAVE & TOP_ING_SLAVE

RD_DATA comprises the transmit and receive portions of the interface. They were developed so that they may be instantiated either separately in different PGAs or together in one FPGA. RD_DATA uses the common sub-modules FIFO_16 & FIFO_8, for simplicity and reliability.

EGR_UTOPIA3_SLAVE

The Egress Slave is responsible for replying to polls from the master in order to receive cells from the master device.

ING_UTOPIA3_SLAVE

The Ingress Slave is responsible for responding to the master in order to send cells to the master device.
FIFO_16 / FIFO_8

The FIFO module contains one FIFO per PHY polled (i.e. this module is instantiated N = number of PHY ports times in each direction. The FIFOs are created by utilizing the available RAM resources in the FPGA. Additionally, two FIFO_16 modules (and hence 2x the RAMs) are instantiated to create a 32-bit wide FIFO for the 32-bit mode, however 2x the cells can be buffered. The FIFO may be operated in synchronous (same clock for read & write) and asynchronous (different clocks for read & write) systems.