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RM7000A

Features: • Dual issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance• 300, 350, 400 MHz operating frequency• >600 Dhrystone 2.1 MIPS @ 400 MHz• High-performance system interface• 1000 MB per second peak ...

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RM7000A: Features: • Dual issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance• 300, 350, 400 MHz operating frequency• >600 D...

RM7000A Data Sheet

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Part Number:
RM7000A
Supply Ability:
5000

Price Break

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Dual issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance
• 300, 350, 400 MHz operating frequency
• >600 Dhrystone 2.1 MIPS @ 400 MHz
• High-performance system interface
• 1000 MB per second peak throughput
• 125 MHz max. freq., multiplexed address/data
• Supports two outstanding reads with out-of-order return
• Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
• Integrated primary and secondary caches
• All are 4-way set associative with 32 byte line size
• 16 KB instruction, 16 KB data, 256 KB on-chip secondary
• Per line cache locking in primaries and secondary
• Fast Packet Cache™ increases system efficiency in networking applications
• Integrated external cache controller (up to 8 MB)
• High-performance floating-point unit - 800 MFLOPS maximum
• Single cycle repeat rate for common single-precision operations and some double-precision operations
• Single cycle repeat rate for single-precision combined multiply-add operations
• Two cycle repeat rate for double-precision multiply and double-precision combined multiply-add operations
• MIPS IV superset instruction set architecture
• Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution
• Single-cycle floating-point multiply-add
• Integrated memory management unit
• Fully associative joint TLB (shared by I and D translations)
• 64/48 dual entries map 128/96 pages
• Variable page size
• Embedded application enhancements
• Specialized DSP integer Multiply-Accumulate instructions, (MAD/MADU) and three-operand multiply instruction (MUL)
• I&D Test/Break-point (Watch) registers for emulation & debug
• Performance counter for system and software tuning & debug
• Fourteen fully prioritized vectored interrupts - 10 external, 2 internal, 2 software
• Fully static CMOS design with dynamic power down logic
• RM5271 pin compatible, 304 pin TBGA package, 31x31 mm


Specifications

Symbol Rating Limits Unit
VTERM Terminal Voltage with respect to VSS 0.52 to +3.9 V
TCASE Operating Temperature
Commercial 0 to +85
Industrial 40 to +85
TSTG Storage Temperature 55 to +125
IIN DC Input Current3 ±20 mA
IOUT DC Output Current4 ±20 V
Notes
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VIN minimum = -2.0 V for pulse width less than 15 ns. VIN should not exceed 3.9 Volts.
3. When VIN < 0V or VIN > VccIO
4. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.


Description

PMC-Sierra's RM7000A is a highly integrated symmetric superscalar microprocessor capable of issuing two instructions each processor cycle. It has two high-performance 64-bit integer units as well as a high-throughput, fully pipelined 64-bit floating point unit.

The RM7000A integrates 16 KB 4-way set associative instruction and data caches along with an integrated 256 KB 4-way set associative secondary. The primary data and secondary caches are write-back and non-blocking. An optional external tertiary cache provides high-performance capability even in applications with very large data sets.

The memory management unit RM7000A contains a 64/48-entry fully associative TLB and a 64-bit system interface supporting multiple outstanding reads with out-of-order return and hardware prioritized and vectored interrupts.

The RM7000A ideally suits high-end embedded control applications such as internetworking, high-performance image manipulation, high-speed printing, and 3-D visualization. The RM7000A is also applicable to the low end workstation market where its balanced integer and floating-point performance and direct support for a large tertiary cache (up to 8 MB) provide outstanding price/ performance.




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