RMPA1901-53

The following describes a procedure for evaluating the RMPA1901-53, a monolithic high efficiency power amplifier,in a  urface mount package, designed for use in Personal Communication Systems (PCS) utilizing Code Division ultiple  ccess (CDMA).  Figure 2 shows the functional block diagram of the packaged product.  Figure 1 shows the  package  utline  and  the  pin  designations.    It  should  be  noted  that  RMPA1901-53  requires  external   assive  omponents for DC bias and RF output matching circuits. A recommended schematic of circuits is shown in Figure 3.  The gate biases for the three stages of the amplifier are set by simple resistive voltage dividers. Potentiometers R1 to R3 are used to set the required quiescent currents of the amplifier stages.  Figure 4 shows a typical layout of an evaluation board, corresponding to the schematic circuits of figure 3.  The following should be noted:
(1) Pin designations are as shown in figure 2.
(2) Vg1, Vg2 and Vg3 are the Gate Voltages (negative)applied at the pins of the package
(3) Vgg1, Vgg2 and Vgg3 are the negative supply voltages at the evaluation board terminals
(4) Vd1, Vd2 and Vd3 are the Drain Voltages (positive)applied at the pins of the package
(5) Vdd1, Vdd2 and Vdd3 are the positive supply voltages at the evaluation board terminals

The  RMPA1901-53  is  a  monolithic  high  efficiency  power  amplifier  for  PCS  CDMA  applications.  Performance parameters may be slightly adjusted by "tweaking" the off-chip matching components. The amplifier circuit design is a single ended configuration that utilizes harmonic tuning for increased power added efficiency and linearity. The device uses Raytheon's Pseudomorphic High Electron Mobility Transistor (pHEMT) process.