RTL8139C(L)+

·128 pin QFP/LQFP (pin-to-pin compatible with the RTL8139C(L))
·Software compatible to the RTL8139 series when configured in RTL8139C mode (C mode)
·Supports descriptor-based buffer management when configured in RTL8139C+ mode (C+ mode)
·Supports Microsoft* NDIS5 Checksum Offloads (IP, TCP, UDP), and Largesend Offload in C+ mode
·Supports IEEE802.1Q VLAN tagging in C+ mode
·Supports Transmit (Tx) Priority Queue for QoS, CoS applications in C+ mode
·Integrated Fast Ethernet MAC, PHY and transceiver in one chip
·10Mbps and 100Mbps operation
·Supports 10Mbps and 100Mbps N-way Auto-negotiation operation
·PCI local bus single-chip Fast Ethernet controller
·Compliant to PCI Revision 2.2
·Supports PCI clocks 16.75MHz-40MHz
·Supports PCI target fast back-to-back transaction
·Supports Memory Read Line, Memory Read
   Multiple, Memory Write and Invalidate, and
   Dual Address Cycle, when set to C+ mode.
·Provides PCI bus master data transfers and PCI
   memory space or I/O space mapped data
   transfers of the RTL8139C(L)+'s operational registers
·Supports PCI VPD (Vital Product Data)
·Supports ACPI, PCI power management
·Supports optional PCI multi-function with additional function in slave mode only.
·Supports CardBus. The CIS can be stored in the 93C56 or expansion ROM
·Supports either MII or Boot ROM interface, though
   only one interface can be implemented at a time. Up to
   128K byte Boot ROM interface for both EPROM and
   Flash memory can be supported
·Supports 25MHz crystal or 25MHz OSC as the internal
   clock source. The frequency deviation of either crystal or
  OSC must be within 50 PPM
·C ompliant to PC99 and PC2001 standards
·Supports Wake-On-LAN function and remote wake-up
   (Magic Packet*, LinkChg and Microsoft wake-up frame)
·Supports 4 Wake-On-LAN (WOL) signals (active high,
   active low, positive pulse, and negative pulse)
·Supports auxiliary power-on internal reset, to be ready
   for remote wake-up when main power still remains off
·Supports auxiliary power auto-detect, and sets the
   related capability of power management registers in PCI configuration space
·Includes a programmable, PCI burst size and early Tx/Rx threshold
·Supports a 32-bit general-purpose timer with the
   external PCI clock as clock source, to generate timer-interrupt
·Contains two large (2Kbyte) independent receive (Rx) and transmit (Tx) FIFOs
·Advanced power saving mode when LAN function or wakeup function is not used
·Uses 93C46 (64*16-bit EEPROM) or 93C56
   (128*16-bit EEPROM) to store resource configuration,
   ID parameter, and VPD data. The 93C56 can also be
   used to store the CIS data structure for the CardBus application
·Supports LED pins for various network activity indications
·Supports digital and analog loopback capability on both ports
·Half/Full duplex capability
·Supports Full Duplex Flow Control (IEEE 802.3x)
·3.3V power supply with 5V tolerant I/Os
    Third-party brands and names are the property of their
respective owners.

The Realtek RTL8139C(L)+ is a highly integrated and cost-effective single-chip Fast Ethernet controller that provides 32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications and IEEE 802.3x Full Duplex Flow Control. It also supports Advanced Configuration Power management Interface (ACPI), PCI power management for modern operating systems that is capable of Operating System Directed Power anagement (OSPM) to achieve the most efficient power management. The RTL8139CL+ is suitable for applications such as CardBus or mobile with built-in network ontroller. The CIS data can be stored in either the 93C56 EEPROM or an external expansion ROM.

In addition to the ACPI feature, the RTL8139C(L)+ also supports remote wake-up (including AMD Magic Packet, LinkChg, and Microsoft wake-up frame) in both ACPI and APM environments. The RTL8139C(L)+ is capable of performing an internal reset through the application of auxiliary power. When auxiliary power is on and the main power remains off, the RTL8139C(L)+ is ready and waiting for the Magic Packet or Link Change to wake the system up. Also, the LWAKE pin provides 4 different output signals including active high, active low, positive pulse, and negative pulse. The versatility of the RTL8139C(L)+ LWAKE pin provides motherboards with the Wake-On-LAN (WOL) function. The RTL8139C(L)+ also supports Analog Auto-Power-down, that is, the analog part of the RTL8139C(L)+ can be shut down temporarily according to user requirements or when the RTL8139C(L)+ is in a power down state with the wakeup function disabled. In addition, when the analog part is shut down and the IsolateB pin is low (i.e. the main power is off), then both the analog and digital parts stop functioning and power consumption of the RTL8139C(L)+ will be negligible. The RTL8139C(L)+ also supports an auxiliary power auto-detect function, and will auto-configure related bits of their own PCI power management registers in PCI configuration space.

The PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies hardware (i.e., the RTL8139C(L)+ LAN card). The information may consist of part number, serial number, and other detailed information. In order to provide a lower cost system, the RTL8139C(L)+ is capable of using a 25MHz crystal as its internal clock source. A 25MHz OSC can also be used.

There are 2 modes of buffer management modes which are supported by the RTL8139C(L)+. The first, C mode, is just like the buffer management algorithm which former RTL8139 series products use; the second is C+ mode (set only by software to the relative C+ mode registers and descriptors) which is an enhanced descriptor-based design especially suitable for server applications. The RTL8139C(L)+ is hardware compatible to the RTL8139C(L), and is software backwards compatible to the RTL8139 series when set to C mode (the default setting). The RTL8139C(L)+ can be configured by software to apply a new
buffer management algorithm, i.e., enhanced descriptor-based buffer management architecture, which is an essential design as a modern network server card.

The RTL8139C(L)+ fully complies to Microsoft NDIS5 (IP, TCP, UDP) Checksum and Segmentation Task-offload features, and supports IEEE802.1Q VLAN (Virtual Bridged Local Area Network). All of the above RTL8139C(L)+ new features contribute to lower CPU utilization, which is a plus when serving as a network server card. Also, the RTL8139C(L)+ boosts its PCI performance by supporting PCI Memory Read Line & Memory Read Multiple when transmitting, Memory Write and Invalidate when receiving. To be better qualified as a server card, the RTL8139C(L)+ also supports the PCI Dual Address Cycle (DAC) command, when the assigned buffers reside at the physical memory addresses higher than 4 Gigabytes. For QoS and CoS requirements, the RTL8139C(L)+ supports hardware high priority queuing to reduce software implementation effort and significantly improve performance.

The RTL8139C(L)+ keeps network maintenance costs low and eliminates usage barriers. It is the easiest way to upgrade a network from 10 to 100Mbps. It also supports full-duplex operation, making 200Mbps of bandwidth possible at no additional cost. To improve compatibility with other brands' products, the RTL8139C(L)+ is also capable of receiving packets with InterFrameGap no less than 40 Bit-Time. The RTL8139C(L)+ is highly integrated and requires no "glue" logic or external memory. It includes an interface for a boot ROM and can be used in diskless workstations, providing maximum network security and ease of management. For special applications, the RTL8139C(L)+ also supports an MII interface, which can be used, for example, to provide a redundant link with an external PHYceiver, or a connection to a Fiber channel with a Fiber transceiver. Because of pin count limitation, the RTL8139C(L)+ does not support a Boot ROM interface when the MII interface is used, and vice versa.