S-24C08A

The S-24C08A has the following features including Data retention: 10 years;Write protection (S-24C08A, S-24C16A);S-24C08A: 8 kbits;S-24C16A: 16 kbits;Sequential read capable.

The S-24C08A is a series of 2-wired, low power 8K/16K-bit EEPROMs with a wide operating range. They are organized as 1K-word ×8-bit, 2K-word × 8-bit respectively. Each is capable of page write, and sequential read.The time for byte write and page write is the same, i. e., 1 msec. (max.)during operation at 5 V ± 10%.Connect pins A2 to the GND or the VCC to assign slave addresses. There are 2 different ways to assign slave addresses in the S-24C08A. The S-24C16A doesn't have address input, so the slave address cannot be input. When the input slave address coincides with the slave address transmitted from the master device, 1 device can be selected from among multiple devices connected to the bus. Always connect the address input pin to GND or VCC and leave it unchanged.For recognition of the address pointer inside the EEPROM, take into consideration the following:The memory address counter inside the EEPROM is automatically incremented for every falling edge of the SCL clock by which the 8th bit of data is output during the time of reading. During the time of writing, upper bits of the memory address (upper 4 bits of the word address and page address) are left unchanged and are not incremented.

S-24C08A Acknowledgment polling is used to know when the rewriting of the EEPROM is finished.
After the S-24C08A EEPROM receives the stop condition signal and once it starts to rewrite, all operations are prohibited. Also, the EEPROM cannot respond to the signal transmitted by the master device.Accordingly, the master device transmits the start condition signal and the device address read/write instruction code to the EEPROM (namely, the slave device) to detect the response of the slave device. This allows users to know when the rewriting of the EEPROM is finished.