S19250

Features: • Operational from 9.9 Gbps to 11.3 Gbps• Built-In Self Test (BIST) with Error Counter• On-chip High-Frequency PLLs for Clock Recovery and Clock Gen.• 16-bit LVDS Parallel Data Path• TX and RX Lock Detect Indicators• Reference Loop Timing Modes• ...

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S19250 Picture
SeekIC No. : 004481348 Detail

S19250: Features: • Operational from 9.9 Gbps to 11.3 Gbps• Built-In Self Test (BIST) with Error Counter• On-chip High-Frequency PLLs for Clock Recovery and Clock Gen.• 16-bit LVDS P...

floor Price/Ceiling Price

Part Number:
S19250
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/26

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Product Details

Description



Features:

• Operational from 9.9 Gbps to 11.3 Gbps
• Built-In Self Test (BIST) with Error Counter
• On-chip High-Frequency PLLs for Clock Recovery and Clock Gen.
• 16-bit LVDS Parallel Data Path
• TX and RX Lock Detect Indicators
• Reference Loop Timing Modes
• Line and Diagnostic Loopback Mode for Faulty Node Identification
• -40°C to 85°C Industrial Temperature Range
• Supports MDIO, I2C and SPI serial interface
• Complies with applicable OIF SFI-4 Phase 1, Telcordia/ITU-T, 300-pin MSA, IEEE 802.3ae and XFP MSA Standards
• 2000 V ESD rating on low speed pins, 1000 V on high speed I/Os
• 17 x 17 mm2, 1.0 mm pitch package with Green / RoHS compliant lead free option. Pin Compatible with S19235/S19237.
• 1.1 W typical



Application

• SONET/SDH and 10GbE-Based Transmission
   Systems & Modules
• Section Repeaters
• Add Drop Multiplexers (ADM)
• Broad-Band Cross-Connects
• Fiber Optic Test Equipment



Description

The S19250 MUX/DeMux chip is a fully integrated serialization/de-serialization SONET STS-192/10 GB Ethernet/Fiber Channel  transceiver with Electronic Dispersion Compensation (EDC). This device can be used to compensate channel impairments caused by Single Mode Fiber (SMF) and copper medium. The chip performs all necessary parallel-to-serial and serial-to-parallel functions in conformance with SONET/SDH, 10 Gigabit Ethernet (10 GbE) and 10 Gigabit Fibre Channel (10 G FC) transmission standards. The figure below shows a typical network application. The other application block diagrams are shown on page 2.

On-chip clock synthesis PLL components are contained in the S19250 chip, allowing the use of a slower external transmit clock reference. The chip can be used with 155.52 MHz or 622.08 MHz (or equivalent FEC/10 GbE/10 G FC rates) reference clocks, in support of existing system clocking schemes. The low-jitter LVDS interface guarantees compliance with the biterror rate requirements of the Telcordia and ITUT standards.

 




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