S2102

The S2102 facilitates high-speed serial transmission of data in a variety of applications including Fibre Channel, serial backplanes, and proprietary point to point links. The chip provides two separate transceivers which are operated individually for a data capacity of >2 Gbps.

Each bi-directional channel provides parallel to serial and serial to parallel conversion, clock generation/ recovery, and framing. The on-chip transmit PLL synthesizes the high-speed clock from a low-speed reference. The on-chip dual receive PLL is used for clock recovery and data re-timing on the two independent data inputs. The transmitter and receiver each support differential PECL-compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a 3.3V power supply and dissipates 1.85 watts.

Figure 1 shows the S2102 and S2002 in a Fibre Channel application. Figure 2 summarizes the input/ output signals of the device. Figures 3 and 4 show the transmit and receive block diagrams, respectively.