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S3025

Features: • Complies with ANSI, Bellcore, and ITU-T specifications for jitter tolerance, jitter transfer and jitter generation• On-chip high frequency PLL with internal loop filter for clock recovery• Supports clock recovery for OC-12/STM-4 (622.08 Mbit/s) NRZ data• 12.96 M...

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SeekIC No. : 004481903 Detail

S3025: Features: • Complies with ANSI, Bellcore, and ITU-T specifications for jitter tolerance, jitter transfer and jitter generation• On-chip high frequency PLL with internal loop filter for c...

S3025 Data Sheet

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Part Number:
S3025
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Complies with ANSI, Bellcore, and ITU-T
   specifications for jitter tolerance,
   jitter transfer and jitter generation
• On-chip high frequency PLL with internal
   loop filter for clock recovery
• Supports clock recovery for OC-12/STM-4
   (622.08 Mbit/s) NRZ data
• 12.96 MHz reference frequency
• Lock detect-monitors run length and frequency
• 350mW typical power dissipation
• Low-jitter PECL interface
• On-chip crystal oscillator allows use of low cost reference crystal
• Micro-power Bipolar technology
• 5V supply
• Available in die form or 20 TSSOP package


Specifications

Parameter Min Typ Max Units
Case Temperature under Bias -55   +125 °C
Junction Temperature under Bias -55   +150 °C
Storage Temperature -65   +150 °C
Voltage on VCC with Respect to GND -0.5   +7.0 V
Voltage on any LVTTL Input Pin -0.5   VCC V
Voltage on any LVPECL Input Pin V CC
2.0		   VCC V
TTL Output Sink Current     20 mA
TTL Output Source Current     10 mA
High Speed LVPECL Output Source Current     50  
Static Discharge Voltage   500   mA



Description

The function of the S3025 clock recovery unit is to derive high speed timing signals for SONET/SDHbased equipment. The S3025 is implemented using AMCC's proven Phase Locked Loop (PLL) technology.

The S3025 receives an OC-12/STM-4 scrambled NRZ signal and recovers the clock from the data. The chip outputs a differential PECL bit clock and retimed data.

The S3025 utilizes an on-chip PLL which consists of a phase detector, a loop filter, and a voltage controlled oscillator (VCO). The phase detector compares the phase relationship between the VCO output and the serial data input. A loop filter of S3025 converts the phase detector output into a smooth DC voltage, and the DC voltage is input to the VCO whose frequency is varied by this voltage. A block diagram is shown in Figure 2.




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