S3067

The S3067 SONET/SDH transceiver chip is designed as a fully integrated multirate serialization/deserialization SONET OC-48, OC-24, OC-12 and OC-3 interface device. The S3067 performs all necessary serial-to-parallel and parallel-to-serial functions in conformance with SONET/SDH transmission and forward error correction (FEC) standards.

S3067 has many features. (1)FEC capability up to 8 bytes per 255-byte block. (2)Reference frequency 131.25MHz to 178MHz. (3)Interface to LVPECL and TTL logic. (4)160-bit single-ended LVPECL data path. (5)Compact 156 pin TBGA package. (6)Diagnostic loopback mode. (7)Supports line timing. (8)Lock detect. (9)Low jitter LVPECL interface. (10)Internal FIFO to decouple transmit clocks. (11)Single 3.3V supply. (12)Typical power 1.5W. And so on.

Some absolute maximum ratings of S3067 have been concluded into several points as follow. (1)Its storage temperature range would be from -65°C to 150°C. (2)Its voltage on Vcc with respect to GND would be from -0.5V to 3.6V. (3)Its voltage on any LVPECL input pin would be from 0V to Vcc. (4)Its high speed LVPECL output source current would be max 24mA. It should be noted that stresses above those listed in absolute maximum ratings may cause permanent damage to S3067.

Also some LVTTL input output DC electrical characteristics of S3067 are concluded as follow. (1)Its input high voltage would be min 2.0V and max TTL Vcc. (2)Its input low voltage would be min 0V and max 0.8V. (3)Its input high current would be max 50uA. (4)Its input low current would be min -500uA. (5)Its output high voltage would be min 2.4V. (6)Its output low voltage would be max 0.5V. (7)Its diff input voltage swing would be min 400mV and max 2400mV. (8)Its single ended input voltage swing would be min 200mV and max 1200mV. And so on. At present we have not got so much information about this IC and we would try hard to get more information about it. If you have any question or suggestion or want to know more information about S3067 please contact us for details. Thank you!