Features: This section will explain the features of the S3C24A0A. Figure 1-1 is an overall block diagram of the S3C24A0A.DescriptionThe S3C24A0A is a 16/32-bit RISC microprocessor, designed to provide a cost-effective, low power, and high performance micro-controller solution for mobile phones and...
S3C24A0A: Features: This section will explain the features of the S3C24A0A. Figure 1-1 is an overall block diagram of the S3C24A0A.DescriptionThe S3C24A0A is a 16/32-bit RISC microprocessor, designed to provi...
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The S3C24A0A is a 16/32-bit RISC microprocessor, designed to provide a cost-effective, low power, and high performance micro-controller solution for mobile phones and general applications. To provide a sufficient H/W performance for the 2.5G & 3G communication services, the S3C24A0A adopts dual-32-bit bus architecture and includes many powerful hardware accelerators for the motion video processing, serial communications, and etc. For the real time video conferencing, an optimized MPEG4 H/W Encoder/Decoder is integrated.
To reduce total system cost and enhance overall functionality, the S3C24A0A also includes following components: separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD controller (TFT), Camera Interface, MPEG-4 ME, MC, DCTQ, NAND Flash Boot loader, System Manager (power management & etc.), SDRAM controller, 2-ch UART, 4-ch DMA, 4-ch Timers, General I/O Ports, IICBUS interface, USB Host, SD Host & Multi-Media Card Interface, Memory Stick Interface, PLL for clock generation & etc. The S3C24A0A can be used as a most powerful Application Processor for mobiles phones. For this application, the S3C24A0A has a Modem Interface to communicate with various Modem Chips.
The S3C24A0A is developed using an ARM926EJ-S core, advanced 0.13um CMOS standard cells and memory compliers. Its low-power, simple, elegant and fully static-design scheme is particularly suitable for cost-sensitive and power-sensitive applications. Also, the S3C24A0A adopts a de-facto standard bus architecture the AMBA (Advanced Microcontroller Bus Architecture).
One of the outstanding features of the S3C24A0A is it's CPU core, a 16/32-bit ARM926EJ-S RISC processor designed by ARM, Ltd. The ARM926EJ-S is a single chip MCU and Java enabled microprocessor. The ARM926EJ-S also implements the MMU, the AMBA BUS, and the Harvard cache architecture with separate 16KB instruction and 16KB data caches, each cache with an 8-word line length.
By providing a complete set of common system peripherals, the S3C24A0A minimizes overall system costs and
eliminates the need to configure additional components.