S3C2501X

Features:

ARM940T Core processor
`  Fully 16/32-bit RISC architecture.
`  Harvard cache architecture with separate 4KB Instruction and Data cache
`  Protection unit to partition memory and set individual protection attributes for each partition
`  AMBA Bus architecture
`  Up to 166MHz operating frequency

Memory Controller
`  24-bit External Address Pins
`  2 Banks for SDRAM with 16/32 bit external bus.
`  8 Banks for Flash/ROM/SRAM/External I/O with 8/16/32-bit external bus.
`  One External Bus Master with Bus Request/Acknowledge Pins

Ethernet Controllers
`  Buffered DMA (BDMA) engine using burst mode
`  BDMA Tx/Rx buffers (256-byte/256-byte)
`  MAC Tx/Rx FIFOs (80-byte/16-byte) to support re-transmit after collision without DMA request
`  Data alignment logic
`  Support for old and new media (compatible with existing 10M-bit/s networks)
`  10/100 Mbps operation to increase price/performance options and to support phased conversions
`  Full IEEE 802.3 compatibility for existing applications
`  Media Independent interface (MII) or 7-wire

On-chip CAM (21 addresses)
`  Full-duplex mode for doubled bandwidth
`  Pause operation hardware support for fullduplex flow control
`  Long packet mode for specialized environments
`  Short packet mode for fast testing
`  PAD generation for ease of processing and reduced processing time interface
`  Station management (STA) signaling for external physical layer configuration and link negotiation

Universal Asynchronous Receiver Transmitter (UART)
`  Programmable baud rates
`  32-byte Transmit FIFO and 32-byte Receive FIFO
`  UART source clock selectable (Internal clock :PCLK2, External clock: EXT_CLK)
`  Auto baud rate detection
`  Infra-red (IR) transmit/receive
`  Insertion of one or two Stop bits per frame
`  Selectable 5-bit, 6-bit, 7-bit, or 8-bit data transfers
`  Parity checking

DES/3DES Accelerator
`  DES or Triple DES mode
`  ECB or CBC mode
`  Encryption or decryption support
`  General DMA support

General DMA Channels
`  Six GDMA channels
`  Memory to memory data transfer
`  Memory to peripheral data transfer (high-speed UART and DES)
`  Support for four external GDMA requests from GDMA request pins (xGDMA_Req0 - xGDMA_Req3).

Six Programmable Timers
`  Interval or toggle mode operation

Hardware Watchdog Timer
`  Useful for periodic reset or interrupts

Programmable Interrupt Controller
`  28 programmable interrupt sources
`  22 internal sources and 6 external sources
`  programmable priority control

Programmable I/O port Controller
`  64 programmable I/O ports
`  Individually configurable to input, output, or I/O mode for dedicated signals
`  6 external interrupt request
`  4 external GDMA request
`  4 external GDMA acknowledge
`  6 timer outputs
`  7 UART signals

I²C Controller
`  Master mode operation only
`  Baud rate generator for serial clock

Three PLLs for System, Core and PHY Clock Each

PLL0 for ARM940T
`  The Input frequency is 10MHz.
`  Provide up to 166MHz output to ARM940T

PLL1 for system clock
`  The Input frequency is 10MHz.
`  Provide up to 133MHz output to system

PLL2 for PHY
`  The input frequency is 10MHz
`  Provide 20 MHz or 25MHz output to external PHY chip

Operating Voltage Range
`  Internal Power: 1.8 V ± 5 %
`  I/O Power: 3.3 V ± 5 %

Operating temperature range
`  -40 85

Package Type
`  272 BGA


Specifications

Symbol	Parameter	Rating		Unit
VDD	DC Supply Voltage	1.8V VDD	2.7	V
		3.3V VDD	3.8
VIN	DC Input Voltage	3.3V input buffer	3.8
VOUT	DC Output Voltage	3.3V Output buffer	3.8
ILATCH	Latch-up current	± 200		mA
TSTG	Storage Temperature	65 to 150

Description

Samsung's S3C2501X 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems, for example, SOHO router, internet gateway, WLAN AP, etc. A variety of communication features are embedded into S3C2501X required in many communication areas, including two Ethernet MACs, a high speed UART, and a console UART. A security feature is also supported by DES/3DES accelerator. This highly integrated microcontroller enables customers to save system costs and increase performance over other 32-bit microcontroller.

The S3C2501X is built based on an outstanding CPU core: The ARM940T cached processor is a member of the ARM9 Thumb family of high-performance 32-bit system-on-a-chip processor solutions. S3C2501X provides a complete high performance CPU subsystem, including ARM9TDMI RISC integer CPU, 4KB instruction/data caches, write buffer, and protection unit, with an AMBA bus interface. The ARM9TDMI core within the ARM940T executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off between high performance and high code density.
It is binary compatible with ARM7TDMI, ARM10TDMI, and Strong ARM processors, and is supported by a wide range of tools, operating systems, and application software.

The following integrated on-chip S3C2501X functions are described in detail in this user's manual :

·  ARM940T cached processor
·  Ethernet Controller
·  GDMA Controller
·  UART Controller
·  I²C Controller
·  Programmable I/O ports
·  Interrupt Controller