S93463

Features:

• Precision Monitor & RESET Controller
- RESET and RESET Outputs
- Guaranteed RESET Assertion to VCC = 1V
- 150ms Reset Pulse Width
- Internal 1.26V Reference with ±1% Accuracy
- ZERO External Components Required
• Memory
- 1K-bit Microwire Memory
- S93462
Internally Ties ORG Low
100% Compatible With all 8-bit
Implementations
Sixteen Byte Page Write Capability
- S93463
Internally Ties ORG High
100% Compatible With all 16-bit
Implementations
Eight Word Page Write Capability


Pinout




Specifications

Temperature Under Bias .................................................................................. 55 to +125
Storage Temperature ....................................................................................... 65 to +150
Voltage on any Pin with Respect to Ground⁽¹⁾ ......................................... 2.0V to +V_CC +2.0V
VCC with Respect to Ground .............................................................................. 2.0V to +7.0V
Package Power Dissipation Capability (Ta = 25) .............................................................. 1.0W
Lead Soldering Temperature (10 secs) ............................................................................ 300
Output Short Circuit Current⁽²⁾ ......................................................................................... 100 mA

Description

The S93462/463 provides a precision reset controller that ensures correct system operation during brownout and power-up/-down conditions. S93462/463  is configured with two open drain reset outputs; pin 7 is an active high output and pin 6 is an active low output.

During power-up, the reset outputs remain active until VCC reaches the VTRIP threshold. The outputs will continue to be driven for approximately 150ms after reaching VTRIP. The reset outputs of S93462/463  will be valid so long as VCC is 1.0V. During power-down, the reset outputs will begin driving active when VCC falls below VTRIP.

The reset pins are I/Os; therefore, the S93462/463 can act as a signal conditioning circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset time-out after detecting a low to high transition and the RESET# input will initiate a reset time-out after detecting a high to low transition. Refer to the applications Information section for more details on device operation as a debounce/reset extender
circuit.

S93462/463  should be noted the reset outputs are open drain. When used as outputs driving a circuit they need to be either tied high (RESET#) or tied to ground (RESET) through the use of pull-up or pull-down resistors. Refer to the applications aid section for help in determining the value of resistor to be used. Internally these pins are weakly pulled up (RESET#) and pulled down (RESET): therefore, if the signals are not being used the pins may be left unconnected.