SA2030

The SA2030 is designed to interface PCM-30 routes with switching systems. The devicesynchronises with the frame-format of the incoming data, and outputs this data inaccordance with the bit and frame timing of the terminating equipment. The circuit is esigned to tolerate delay, drift, wander and jitter of the incoming data and clock, and thus implifies the design of data- and clock-recovery hardware. The internal 1½ frames lastic buffer provides for delay compensation and wander immunity. If the bounds of he buffer are exceeded, the SA2030 will either repeat or drop a frame. The circuit will accurately detect incoming Alarm-Indication-Signal (AIS) conditions, in accordance withCCITT recommendation G.737. Loss of frame alignment is indicated on both dedicated utputs and by outputting of AIS. The circuit includes a bidirectional alarm port forinterrogation of alarm conditions.