SA8028

The SA8028 BICMOS device integrates programmable dividers, charge pumps and phase comparators to implement phaselocked loops. The device is designed to operate from 3 NiCd cells, in pocket phones, with low current and nominal 3 V supplies.

The synthesizer operates at VCO input frequencies up to 2.5 GHz. The synthesizer has fully programmable RF, IF, and reference dividers. All divider ratios are supplied via a 3-wire serial programming bus. The RF divider is a fractional-N divider with programmable integer ratios from 33 to 509 and a fractional resolution of 22 programmable bits (23 bits internal). A 2nd order sigma-delta modulator is used to achieve fractional division.

Separate power and ground pins are provided to the charge pumps and digital circuits. V_DDCP must be equal to or greater than V_DD. The ground pins should be externally connected to prevent large currents from flowing across the die and thus causing damage.

The charge pump current (gain) is fully programmable, while ISET is set by an external resistance at the R_SET pin (refer to section 1.5, RF and IF Charge Pumps). The phase/frequency detector charge pump outputs allow for implementing a passive loop filter.