SAA6721E Selling Leads, Price trend, SAA6721E DataSheet download, circuit diagram from SeekIC.com

Features: 1.1 RGB video input· Digital single (24-bit) or dual (48-bit) channel RGB input· Data input of sampled RGB data with a pixel frequency of maximum 150 MHz· Free definable data acquisition offsets and vertical window size in single pixel increments, horizontal window size in double pixel i...

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SeekIC No. : 004483959 Detail

SAA6721E: Features: 1.1 RGB video input· Digital single (24-bit) or dual (48-bit) channel RGB input· Data input of sampled RGB data with a pixel frequency of maximum 150 MHz· Free definable data acquisition o...

SAA6721E Data Sheet

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Part Number:: SAA6721E
Supply Ability:: 5000

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Qty
1~5000

Unit Price
Negotiable

Processing time
15 Days

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Upload time: 2026/1/20

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Product Details

Description

Features:

1.1 RGB video input
· Digital single (24-bit) or dual (48-bit) channel RGB input
· Data input of sampled RGB data with a pixel frequency of maximum 150 MHz
· Free definable data acquisition offsets and vertical window size in single pixel increments, horizontal window size in double pixel increments
· Programmable pulses for ADC clamping and ADC gain correction
· Detection of presence of sync signals, and of their polarities
· Support for auto-adjustment functions for sample clock frequency, phase, vertical and horizontal sample offset, as well as colour adjustment
· Maximum supported resolution of 1280× 1024 dots Super Extended Graphics Adapter (SXGA)
· Support for detection of the applied graphics mode (multi-sync).
1.2 YUV video input
· Pin sharing between YUV and RGB input port
· YUV 4 : 4 : 4, YUV 4 : 2 : 2, YUV 4 : 2 : 2 with CCIR 656 codes, YUV 4 : 1 : 1 input of interlaced and non-interlaced digital video data
· Maximum picture resolution of 1024 ×1024 pixels for interlaced or non-interlaced video
· Input of video data at maximum 75 MHz
· Free definable data acquisition offsets and window in double pixel or single line increments
· YUV to RGB colour space conversion.
1.3 Video processing
· Colour correction Look-Up Table (LUT)
· Phase correct up and downscaling of the RGB data
· Fully programmable scaling ratios
· Independent horizontal and vertical scaling engine
· Free definable position of the scaled input picture inside the output picture with programmable border colour
· De-interlacing unit for digital YUV video data
· Zoom up to full-screen resolution of the de-interlaced YUV video stream via the main scaler.
1.4 On screen display
· Character based internal On Screen Display (OSD)
· Programmable character matrix sizes of either 24 × 24 pixels (42 characters available) or 12 ×16 pixels (128 characters available)
· Programmable width and height of the OSD window, built from maximum 1152 characters
· 8 different colours for foreground and background inclusive transparent colours
· Overlay port for external OSD controller.
1.5 Video output
· Single pixel/clock (24-bit) or double pixel/clock (48-bit) digital RGB output
· Generation of synchronization and validation signals for the Thin Film Transistor (TFT) display
· Frame rate control (temporal dithering) for displaying true colour graphics on high colour displays
· Free programmable timing for displays of several manufacturers.
1.6 Memory interface
· Support of both 1M × 16 SDRAM, 256k ×32 SGRAM or 128k ×32 SGRAM devices
· Maximum memory clock frequency of 125 MHz
· Scalable memory size built of either 2, 3 or 4 SDRAM, or of 1 or 2 SGRAM devices
· Special mode for operation without external memory.
1.7 Miscellaneous
· Internal Phase-Locked Loop (PLL) for memory and panel clock generation from the system clock
· I²C-bus interface with 2 selectable addresses
· Boundary scan test circuit and Joint Test Action Group (JTAG) test controller.

Specifications

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
V_DDD	digital supply voltage		-0.5	+4.6	V
V_DD(PLL)	PLL supply voltage		-0.5	+4.6	V
V_n	voltage at digital inputs and outputs	outputs in 3-state	-0.5	+5.5	V
V_n	voltage at digital output	outputs active	-0.5	V_DDD + 0.5	V
V_SS	voltage difference between V_SS(PLL) and V_SS(D)		-	100	mV
T_stg	storage temperature		-65	+150	°C
T_amb	ambient temperature		0	70	°C
T_amb(bias)	operating bias ambient temperature		-10	+70	°C
V_es	electrostatic handling voltage for all pins	note 1	-2	+2	kV

Note
1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kW resistor.

Description

The SAA6721E is a graphics engine, which converts digital RGB or YUV data into video signals suitable for TFT displays. SAA6721E supports SXGA input resolution as well as true colour. Independent horizontal and vertical up and downscaling can display the input data arbitrarily on the connected TFT display. Multi-sync capability allows the applied graphics mode to be detected.

Overlay signals of SAA6721E can be generated either by an internal OSD generator or supplied via the overlay port from an external OSD controller.

The SAA6721E must be embedded into a system containing a microcontroller with an I2C-bus serial interface. For multi-sync capabilities a frame buffer built from SGRAM or SDRAM is needed. The size of this frame buffer SAA6721E depends on the maximum resolution and bandwidth needed for the application. For converting the analog RGB stream into a digital data stream one or two ADCs with 3 channels each for R, G and B are needed. If the YUV input is used, a video front-end chip such as the SAA7113 must be used in front of the YUV port.

SAA6721E

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