SC68C562

Features: • Full hardware and software upward compatibility with previous NMOS devicePinoutSpecifications SYMBOL PARAMETER RATING UNIT COMMERCIAL INDUSTRIAL TA Operating ambient temperature2 0 to +70 -40 to +85 TSTG Sto...

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SeekIC No. : 004485680 Detail

SC68C562: Features: • Full hardware and software upward compatibility with previous NMOS devicePinoutSpecifications SYMBOL PARAMETER RATING UNIT COMMERCIAL INDUSTRIA...

floor Price/Ceiling Price

Part Number:
SC68C562
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/19

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Product Details

Description



Features:

• Full hardware and software upward compatibility with previous NMOS device


Pinout

  Connection Diagram


Specifications

SYMBOL

PARAMETER

RATING

UNIT

COMMERCIAL
INDUSTRIAL

TA


Operating ambient temperature2

0 to +70

-40 to +85

 

TSTG

Storage temperature

-65 to +150

-65 to +150

 

VCC


voltages from  VCC to GND3

-0.5 to +7.0

0.5 to +7.0

V

VS

Voltage from any pin to ground3

-0.5 to V CC+0.5

-0.5 to V CC+0.5

V




Description

The Philips Semiconductors SC68C562 Dual Universal Serial Communications Controller (CDUSCC) is a single-chip CMOS-LSI communications device that provides two independent, multi-protocol, full-duplex receiver/transmitter channels in a single package. It supports bit-oriented and character-oriented (byte count and byte control) synchronous data link controls as well as asynchronous protocols. The SC68C562 interfaces to the 68000 MPUs via asynchronous bus control signals and is capable of program-polled, interrupt driven, block-move or DMA data transfers.

The SC68C562 is hardware (pin) and software (Register) compatible with SCN68562 (NMOS version). It will automatically configure to NMOS DUSCC register map on power-up or reset.

The operating mode and data format of each channel can be programmed independently. Each channel consists of a receiver, a transmitter, a 16-bit multifunction counter/timer, a digital phase-locked loop (DPLL), a parity/CRC generator and checker, and associated control circuits. The two channels share a common bit rate generator (BRG), operating directly from a crystal or an external clock, which provides 16 common bit rates simultaneously. The operating rate for the receiver and transmitter of each channel can be independently selected from the BRG, the DPLL, the counter/timer, or from an external 1X or 16X clock.

This makes the CDUSCC well suited for dual speed channel applications. Data rates up to 10Mb/s are supported.

Each transmitter and each receiver is serviced by a 16 byte FIFO. The receiver FIFO also stores 9 status bits for each character received; the transmit FIFO is able to store transmitter commands with each byte. This permits reading and writing of up to 16 bytes at a time, thus minimizing the potential for transmitter underrun, receiver overrun and reducing interrupt or DMA overhead.

In addition, a flow control capability is provided to disable a remote transmitter when the FIFO of the local receiving device is full. Two modem control inputs (DCD and CTS) and three modem control outputs (RTS and two general purpose) are provided. Because the modem control inputs are general purpose in nature, they can be optionally programmed for other functions. This document contains the electrical specifications for the SC68C562. Refer to the CMOS
Dual Universal Serial Communications Controller (CDUSCC) User
Manual for a complete operational description of this product.




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