Features: IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test mode. Clock recovery from PLL lock to random data patterns. Guaranteed transition every data transfer cycle Chipset (Tx + Rx) power consumption <500 mW (typ) @66 MHz Single differential pair eliminates multi-channel skew660 Mbps ser...
SCAN921224: Features: IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test mode. Clock recovery from PLL lock to random data patterns. Guaranteed transition every data transfer cycle Chipset (Tx + Rx) power con...
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Serializers & Deserializers (Serdes) Interface IC
US $145.22 - 145.22 / Piece
Interface Development Tools SCAN15MB200 EVAL BOARD
| Function | Deserializer |
| Total Throughput | 660 Mbps |
| Payload/Channel | 660 Mbps |
| Clock Min | 20 MHz |
| Clock Max | 66 MHz |
| Input Compatibility | LVDS/BLVDS |
| Output Compatibility | LVTTL |
| Start/Stop Bit | Yes |
| Power Consumption_ | 363 mW |
| SupplyVoltage | 3.3 Volt |
| ESD | 2 kV |
| Temperature Min | -40 deg C |
| Temperature Max | 85 deg C |
| Compression Ratio | 10:1 |
| Number Receivers | 1 |
| JTAG1149.1 | Yes |
| Communications | Yes |
| Sensing & Imaging | Yes |
| Parallel Bus Width | 10 bits |
| View Using Catalog | |
The SCAN921023 and SCAN921224 are a 10-bit Serializer and Deserializer chipset designed to transmit data over differential backplanes at clock speeds from 20 to 66 MHz. The chipset is also capable of driving data over Unshielded Twisted Pair (UTP) cable.
The chipset SCAN921224 has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two passive states: Powerdown and TRI-STATE. In addition to the active and passive states, there are also test modes for JTAG access and at-speed BIST.
The following sections describe each operation and passive state and the test modes.