Features: IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test mode.
Clock recovery from PLL lock to random data patterns.
Guaranteed transition every data transfer cycle
Chipset (Tx + Rx) power consumption < 600 mW (typ) @ 80 MHz
Single differential pair eliminates multi-channel skew
800 Mbps serial Bus LVDS data rate (at 80 MHz clock)
10-bit parallel interface for 1 byte data plus 2 control bits
Synchronization mode and LOCK indicator
Programmable edge trigger on clock
High impedance on receiver inputs when power is off
Bus LVDS serial output rated for 27 load
Small 49-lead BGA package
Specifications
| Function |
Deserializer |
| Total Throughput |
800 Mbps |
| Payload/Channel |
800 Mbps |
| Clock Min |
30 MHz |
| Clock Max |
80 MHz |
| Input Compatibility |
LVDS/BLVDS |
| Output Compatibility |
LVTTL |
| Start/Stop Bit |
Yes |
| Power Consumption_ |
330 mW |
| SupplyVoltage |
3.3 Volt |
| Eval Kit |
BLVDS03 |
| ESD |
2 kV |
| Temperature Min |
-40 deg C |
| Temperature Max |
85 deg C |
| Compression Ratio |
10:1 |
| Number Receivers |
1 |
| JTAG1149.1 |
Yes |
| Communications |
Yes |
| Sensing & Imaging |
Yes |
| Parallel Bus Width |
10 bits |
| View Using Catalog |
Supply Voltage(VCC) -0.3Vto+4V
LVCMOS/LVTTL Input Voltage-0.3V to (VCC +0.3V)
LVCMOS/LVTTL Output Voltage -0.3V to (VCC +0.3V)
Bus LVDS Receiver Input Voltage -0.3V to +3.9V
Bus LVDS Driver Output Voltage -0.3V to +3.9V
Bus LVDS Output Short Circuit Duration 10mS
Junction Temperature +150
Storage Temperature-65 to +150
Lead Temperature (Soldering, 4 seconds) +220
Maximum Package Power Dissipation Capacity @ 25 Package: 49L BGA 1.47 W
Package Derating: 49L BGA11.8 mW/above +25
ja 85/W
ESD Rating
HBM >2kV
MM > 250V
DescriptionThe SCAN921025 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The SCAN921226 receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and recovers parallel clock.
Both devices are compliant with IEEE 1149.1 Standard for Boundary Scan Test. IEEE 1149.1 features provide the design or test engineer access via a standard Test Access Port (TAP) to the backplane or cable interconnects and the ability to verify differential signal integrity. The pair of devices also features an at-speed BIST mode which allows the interconnects between the Serializer and Deserializer to be verified at-speed.
The SCAN921025 transmits data over backplanes or cable. The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits clock and data bits serially, it eliminates clock-to-data and data-to-data skew. The powerdown pin saves power by reducing supply current when not using either device. Upon power up of the Serializer, you can choose to activate synchronization mode or allow the Deserializer to use the synchronization-to-random-data feature. By using the synchronization mode, the Deserializer will establish lock to a signal within specified lock times. In addition, the embedded clock guarantees a transition on the bus every 12-bit cycle. This eliminates transmission errors due to charged cable conditions. Furthermore, you may put the SCAN921025 output pins into TRI-STATE to achieve a high impedance state. The PLL can lock to frequencies between 30 MHz and 80 MHz.
Reliability Metrics
| Part Number |
Process |
EFR Reject |
EFR Sample Size |
PPM |
LTA Rejects |
LTA Device Hours |
FITS |
MTTF (Hours) |
| SCAN921226SLC |
CMOS8 |
1 |
12195 |
83 |
0 |
1410500 |
3 |
400233226 |
Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.For more information on Reliability Metrics, please click here.
Application Notes
| Title |
Size in Kbytes |
Date |
|
| AN-1217: Application Note 1217 How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask |
339 Kbytes |
2-May-04 |
Download |
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The SCAN921025 and SCAN921226 are a 10-bit Serializer and Deserializer chipset designed to transmit data over differential backplanes at clock speeds from 30 to 80 MHz. The chipset is also capable of driving data over Unshielded Twisted Pair (UTP) cable.
The chipset has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two passive states: Powerdown and TRI-STATE. In addition to the active and passive states, there are also test modes for JTAG access and at-speed BIST.
The following sections describe each operation and passive state and the test modes.
SCAN921226 Data Sheet
