Features: IEEE 1149.1 (JTAG) Compliant Bus LVDS SignalingLow power CMOS design High Signaling Rate Capability (above 100 Mbps) 0.1V to 2.3V Common Mode Range for VID = 200mV ±100 mV Receiver Sensitivity Supports open and terminated failsafe on port pins 3.3V operation Glitch free power up/down (D...
SCAN92LV090: Features: IEEE 1149.1 (JTAG) Compliant Bus LVDS SignalingLow power CMOS design High Signaling Rate Capability (above 100 Mbps) 0.1V to 2.3V Common Mode Range for VID = 200mV ±100 mV Receiver Sensit...
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Interface Development Tools SCAN15MB200 EVAL BOARD

| PHY Type | Transceiver |
| Family | B-LVDS |
| Channels | 9 Channels |
| Max Data Rate | 100 Mbps |
| Input Compatibility | LVTTL/LVDS |
| Output Compatibility | LVTTL/LVDS |
| Power Consumption_ | 429 mW |
| Special Features | Low Skew |
| SupplyVoltage | 3.3 Volt |
| JTAG1149.1 | Yes |
| Temperature Min | -40 deg C |
| Temperature Max | 85 deg C |
| Function | Transceiver |
| View Using Catalog | |
The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector.
The driver SCAN92LV090 translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ±1V.
The receiver threshold SCAN92LV090 is less than ±100 mV over a ±1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels.
This SCAN92LV090 is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and the optional Test Reset (TRST).