SCANPSC100F

The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus. It is useful in improving scan throughput when applying serial vectors to system test circuitry and reduces the software overhead that is associated with applying serial patterns with a parallel processor. The SCANPSC100F operates by serializing data from the parallel bus for shifting through the chain of 1149.1 compliant components (i.e., scan chain). Scan data
returning from the scan chain is placed on the parallel port to be read by the host processor. Up to two scan chains can be directly controlled with the SCANPSC100F via two independent TMS pins. Scan control is supplied with user specific patterns which makes the SCANPSC100F protocol-independent. Overflow and underflow conditions are prevented by stopping the test clock. A 32-bit counter is used to program the number of TCK cycles required to
complete a scan operation within the boundary scan chain or to complete a SCANPSC100F Built-In Self Test (BIST) operation. SCANPSC100F device drivers and 1149.1 embedded test application code are available with Fairchild's SCAN Ease software tools.