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SCANSTA101

Features: Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture Supported by National's SCAN Ease (Embedded Application Software Enabler) Software Rev 2.0 Available as a Silicon Device and Intellectual Property (IP) model for embedding into VLSI devices Uses gene...

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SeekIC No. : 004485849 Detail

SCANSTA101: Features: Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture Supported by National's SCAN Ease (Embedded Application Software Enabler) Software Rev 2.0 Availabl...

SCANSTA101 Data Sheet

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Part Number:
SCANSTA101
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture
Supported by National's SCAN Ease (Embedded Application Software Enabler) Software Rev 2.0
Available as a Silicon Device and Intellectual Property (IP) model for embedding into VLSI devices
Uses generic, asynchronous processor interface; compatible with a wide range of processors and PCLK frequencies
16-bit Data Interface (IP scalable to 32-bit)
2Kx32 bit dual-port memory addressing for access by the PPI or the 1149.1 master
Load-on-the-fly (LotF) and Preload operating modes supported
On-Board Sequencer allows multi-vector operations such as those required to load data into an FPGA
On-Board Compares support TDI validation against preloaded expected data
32-bit Linear Feedback Shift Register (LFSR) at the Test Data In (TDI) port
State, Shift, and BIST macros allow predetermined TMS sequences to be utilized
Operates at 3.3v supply voltages w/ 5V tolerant I/O
Outputs support Power-Down TRI-STATE mode.




Pinout

Connection Diagram




Specifications

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (VCC) −0.5V to +4.0V
DC Input Diode Current (IIK)
VI = −0.5V −20 mA
DC Input Voltage (VI) −0.5V to +4.0V
DC Output Diode Current (IOK)
VO = −0.5V −20 mA
DC Output Voltage (VO) −0.5V to +4.0V
DC Output Source/Sink Current (IO) ±50 mA
DC VCC or Ground Current ±50 mA
per Output Pin
DC Latchup Source or Sink Current±300 mA
Junction Temperature
Plastic+150°C
Storage Temperature −65°C to +150°C
Lead Temperature (Solder, 4sec)
49L BGA 220°C
Max Pkg Power Capacity @ 25°C
49L BGA 1.47W
Thermal Resistance (JA)
49L BGA 85°C/W
Package Derating 11.8mW/°C above +25°C
ESD Last Passing Voltage (Min) 2000V

Temperature Min -40 deg C
Temperature Max 85 deg C
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Description

The SCANSTA101 is designed to function as a test master for a IEEE 1149.1 test system. The minimal requirements to create a tester are a microcomputer (uP, RAM/ROM, clock, etc.), SCANEASE r2.0 software, and a STA101.

The SCANSTA101 is an enhanced version of, and replacement for, the SCANPSC100. The additional features of the STA101 further allow it to offload some of the processor overhead while remaining flexible. The device architecture supports IEEE 1149.1, BIST, and IEEE 1532. The flexibility will allow it to adapt to any changes that may occur in 1532 and support yet unknown variants.

The SCANSTA101 is useful in improving vector throughput when applying serial vectors to system test circuitry and reduces the software overhead that is associated with applying serial patterns with a parallel processor. The SCANSTA101 features a generic Parallel Processor Interface (PPI) which operates by serializing data from the parallel bus for shifting through the chain of 1149.1 compliant components (i.e., scan chain). Writes can be controlled either by
wait states or theDTACK line. Handshaking is accomplished with either polling or interrupts.






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