SCANSTA111

Features: True IEEE 1149.1 hierarchical and multidrop addressable capability The 7 slot inputs support up to 121 unique addresses, an Interrogation Address, Broadcast Address, and 4 Multi-cast Group Addresses (address 000000 is reserved) 3 IEEE 1149.1-compatible configurable local scan ports Mode...

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SeekIC No. : 004485850 Detail

SCANSTA111: Features: True IEEE 1149.1 hierarchical and multidrop addressable capability The 7 slot inputs support up to 121 unique addresses, an Interrogation Address, Broadcast Address, and 4 Multi-cast Grou...

floor Price/Ceiling Price

Part Number:
SCANSTA111
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/26

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Product Details

Description



Features:

True IEEE 1149.1 hierarchical and multidrop addressable capability
The 7 slot inputs support up to 121 unique addresses, an Interrogation Address, Broadcast Address, and 4 Multi-cast Group Addresses (address 000000 is reserved)
3 IEEE 1149.1-compatible configurable local scan ports
Mode Register0 allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three
Transparent Mode can be enabled with a single instruction to conveniently buffer the backplane IEEE 1149.1 pins to those on a single local scan port
LSP ACTIVE outputs provide local port enable signals for analog busses supporting IEEE 1149.4.
General purpose local port passthrough bits are useful for delivering write pulses for FPGA programming or monitoring device status.
Known Power-up state
TRST on all local scan ports
32-bit TCK counter
16-bit LFSR Signature Compactor
Local TAPs can become TRI-STATE via theOE input to allow an alternate test master to take control of the local TAPs (LSP0-2 have a TRI-STATE notification output)
3.0-3.6V VCC Supply Operation
Power-off high impedance inputs and outputs
Supports live insertion/withdrawal






Pinout

  Connection Diagram




Specifications

Temperature Min -40 deg C
Temperature Max 85 deg C
View Using Catalog


Supply Voltage (VCC) −0.3V to +4.0V
DC Input Diode Current (IIK)
VI = −0.5V −20 mA
DC Input Voltage (VI)−0.5V to +3.9V
DC Output Diode Current (IOK)
VO = −0.5V −20 mA
DC Output Voltage (VO) −0.3V to +3.9V
DC Output Source/Sink Current (IO) ±50 mA
DC VCC or Ground Current ±50 mA
per Output Pin
DC Latchup Source or Sink Current ±300 mA
Junction Temperature (Plastic) +150
Storage Temperature −65 to +150
Lead Temperature (Solder, 4sec)
49L BGA 235
48L TSSOP 260°C
Max Pkg Power Capacity @ 25
49L BGA 1.47 W
48L TSSOP 1.47 W
Thermal Resistance (JA)
49L BGA 85/W
48L TSSOP 85/W
Package Derating 11.8 mW/ above
25
ESD Last Passing Voltage (Min)
I/O 2000V
Inputs1000V





Description

The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA111 supports up to 3 local IEEE1149.1 scan rings which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.

Reliability Metrics


Part Number Process EFR Reject EFR Sample Size PPM LTA Rejects LTA Device Hours FITS MTTF (Hours)
SCANSTA111MT CMOS7 0 16561 0 0 954000 4 270700104
SCANSTA111MTX CMOS7 0 16561 0 0 954000 4 270700104
SCANSTA111SM CMOS7 0 16561 0 0 954000 4 270700104
SCANSTA111SMX CMOS7 0 16561 0 0 954000 4 270700104

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.


Application Notes


Title Size in Kbytes Date
AN-1312: Application Note 1312 Scan Bridge (STA111/STA112) Timing 41 Kbytes 7-Jun-04 Download
AN-1312 (Chinese): Application Note 1312 Scan Bridge (STA111/STA112) Timing
138 Kbytes 640){this.height=this.height*640/this.width;this.width=640;}' border="0" alt=" Connection Diagram">
AN-1340: Application Note 1340 Simplified Programming of Xilinx Devices Using a SCANSTA111/112 JTAG Chain Mux 441 Kbytes 13-Jul-05 Download
AN-1340 (Chinese): Application Note 1340 Simplified Programming of Xilinx Devices Using a SCANSTA111/112 JTAG Chain Mux
234 Kbytes 640){this.height=this.height*640/this.width;this.width=640;}' border="0" alt=" Connection Diagram">
AN-1327: Application Note 1327 Simplified Programming of Altera FPGA's using a SCANSTA111/112 Scan Chain Mux 64 Kbytes 2-Sep-04 Download
AN-1259: Application Note 1259 SCANSTA112 Designers Reference 533 Kbytes 7-Aug-08 Download

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