Features: Fast bus cycle times reduce or eliminate CPU wait states Dual full-duplex asynchronous receiver/transmitters Quadruple buffered receiver data registers Programmable data format¤ 5 to 8 data bits plus parity¤ Odd, even, no parity or force parity¤ 1, 1.5 or 2 stop bits programmable in 1/1...
SCC2681T: Features: Fast bus cycle times reduce or eliminate CPU wait states Dual full-duplex asynchronous receiver/transmitters Quadruple buffered receiver data registers Programmable data format¤ 5 to 8 da...
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|
SYMBOL |
PARAMETER |
RATING |
UNIT |
|
Tamb |
Operating ambient temperature range2 |
0 to +70 |
|
|
TSTG |
Storage temperature range |
-65 to +150 |
|
|
|
All voltages with respect to GND3 |
-0.5 to +6.0 |
V |
|
|
Pin voltage range |
VSS -0.5 to V CC+0.5 |
V |
The Philips Semiconductors SCC2681T Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip MOS-LSI communications device that provides two independent full-duplex asynchronous receiver/transmitter channels in a single package. The SCC2681T features a faster bus cycle time than the standard SCC2681. The quick bus cycle eliminates or reduces the need for wait states with fast CPUs and permits high throughput in I/O intensive systems. Higher external clock rates may be used with the transmitter, receiver and counter timer which in turn provide greater versatility in baud rate generation. The SCC2681T interfaces directly with microprocessors and may be used in a polled or interrupt driven system. It is manufactured in CMOS technology.
The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of eighteen fixed baud rates, a 16 clock derived from a programmable counter/timer, or an external 1 or 16 clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems.
Each receiver is quadruple buffered to minimize the potential of receiver over-run or to reduce interrupt overhead in interrupt driven systems. In addition, a flow control capability is provided to disable a remote DUART transmitter when the receiver buffer is full.
Also provided on the SCC2681T are a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control.
For a complete functional description and programming information for the SCC2681T, refer to the SCC2681 product specification.