SCC68692C1A44

Supply Voltage - Max : 5.5 V
Supply Voltage - Min : 4.5 V
Number of Channels : 2
Packaging : Tube
Supply Current : 10 mA
Package / Case : PLCC-44
Data Rate : 115.2 Kbps
Maximum Operating Temperature : + 70 C
Minimum Operating Temperature : 0 C


Pinout




Description

The SCC68692C1A44 is one member of the SCC68692C1A44  series.It has the following features including S68000 bus compatible;Dual full-duplex asynchronous receiver/transmitters;Quadruple buffered receiver data register;Automatic wake-up mode for multidrop applications;Start-end break interrupt/status;Detects break which originates in the middle of a character;On-chip crystal oscillator;Power down mode;Receiver timeout mode;Commercial and Industrial temperature range versions;TTL compatible.

The Philips Semiconductors SCC68692C1A44  Dual Universal Asynchronous Receiver/Transmitter (DUART) is compatible with SCN68681. It is a single-chip CMOS-LSI communications device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. It is compatible with other S68000 family devices and can also interface easily with other microprocessors. The DUART can be used in a polled or interrupt driven systems.The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of eighteen fixed baud rates, a 16X clock derived from a programmable counter/timer,or an external 1X or 16X clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems.

Also provided on the SCC68692C1A44  are a multipurpose 6-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control.The operation control logic receives operation commands from the CPU and generates appropriate signals to internal sections to control device operation. It contains address decoding and read and write circuits to permit communications with the microprocessor via the data bus buffer. The DTACKN output is asserted during write and read cycles to indicate to the CPU that data has been latched on a write cycle, or that valid data is present on the bus on a read cycle.