Features: General Features
- 3.3 Volt Operation (SIO Block is 5 Volt Tolerant)
- LPC Interface
- Programmable Wake-up Event Interface
- PC99, PC2001 Compliant
- ACPI 2.0 Compliant
- Multiplexed Command, Address and Data Bus
- Serial IRQ Interface Compatible with Serialized Support for PCI Systems
- PME Interface
- ISA Plug-and-Play Compatible Register Set
- 25 General Purpose Input/Output Pins
- System Management Interrupt
AC Power Failure Recovery
Watchdog Timer
2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk Controller
- Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core
- Supports One Floppy Drive
- Configurable Open Drain/Push-Pull Output Drivers
- Supports Vertical Recording Format
- 16-Byte Data FIFO
- 100% IBM® Compatibility
- Detects All Overrun and Underrun Conditions
- Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption
- DMA Enable Logic
- Data Rate and Drive Control Registers
- 480 Address, Up to Eight IRQ and Three DMA Options
- Support 3 Mode FDD
Enhanced Digital Data Separator
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Rates
- Programmable Precompensation Modes
Serial Ports
- Two Full Function Serial Ports
- High Speed NS16C550A Compatible UARTs with Send/Receive 16-Byte FIFOs
- Supports 230k and 460k Baud
- Programmable Baud Rate Generator
- Modem Control Circuitry
- 480 Address and 15 IRQ Options
Infrared Port
- Multiprotocol Infrared Interface
- IrDA 1.0 Compliant
- SHARP ASK IR
- 480 Addresses, Up to 15 IRQ
Multi-Mode™ Parallel Port with ChiProtect™
- Standard Mode IBM PC/XT®, PC/AT®, and PS/2™ Compatible Bi-directional Parallel Port
- Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)
- IEEE 1284 Compliant Enhanced Capabilities Port (ECP)
- ChiProtect Circuitry for Protection
- 960 Address, Up to 15 IRQ and Three DMA Options
Keyboard Controller
- 8042 Software Compatible
- 8 Bit Microcomputer
- 2k Bytes of Program ROM
- 256 Bytes of Data RAM
- Four Open Drain Outputs Dedicated for Keyboard/Mouse Status Register
- Supports Interrupt and Polling Access
- 8 Bit Counter Timer
- Port 92 Support
- Fast Gate A20 and KRESET Outputs
Motherboard GLUE Logic
- IDE Reset Output
- (4) Buffered PCI Reset Outputs with software controlled reset capability - default transparent
- 3VSB Gate and 3V Gate signal generation
- Front Panel Reset Debouncing and Power Good Signal Generation
- Power Supply Turn On Circuitry with Support for power button on PS/2 Keyboard
- Resume Reset Signal Generation
- SMBus Isolation Circuitry (2 sets external and 1 set internal for Hardware Monitoring Block)
- SMBus 2.0 compliant interface for Hardware Monitoring
- LED Control (2)DescriptionThe SCH5017 is a 3.3V (Super I/O Block is 5V tolerant) PC99/PC2001 compliant Super I/O controller with an LPC interface. SCH5017 also includes Hardware Monitoring capabilities, enhanced Security features, Power Control logic and Motherboard Glue logic.
The SCH5017's hardware monitoring capability includes temperature, voltage and fan speed monitoring. It has the ability to alert the system to out-of-limit conditions and automatically control the speeds of multiple fans. There are four analog inputs for monitoring external voltages of +5V, +5VTR, +12V and Vccp (core processor voltage), as well as internal monitoring of the SIO's VCC, VTR, and Vbat power supplies. The SCH5017 includes support for monitoring two external temperatures via thermal diode inputs and an internal sensor for measuring ambient temperature. The nHWM_INT pin is implemented to indicate t-of-limit temperature, voltage, and FANTACH conditions. The hardware monitoring block of the SCH5017 is accessible via the System Management Bus (SMBus). The same interrupt event reported on the nHWM_INT pin also creates PME wakeup events and speaker alarm annunciation.
The SCH5017 also allows for a two or three piece linear fan function.
The Motherboard Glue logic includes various power management and system logic including generation of nRSMRST, SMBus buffers, and buffered PCI reset outputs.
The SCH5017 incorporates complete legacy Super I/O functionality including an 8042 based keyboard and mouse controller, an IEEE 1284, EPP, and ECP compatible parallel port, one serial port that is 16C550A UART compatible, one IrDA 1.0 infrared ports, and a floppy disk controller with SMSC's true CMOS 765B core and enhanced digital data separator, The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and is software and register compatible with SMSC's proprietary 82077AA core. System related functionality, which offers flexibility to the system designer, General Purpose I/O control functions, control of two LED's, and fan control using fan tachometer inputs and pulse width modulator (PWM) outputs.
The SCH5017 is ACPI 1.0/2.0 compatible and therefore supports multiple low power-down modes. It incorporates sophisticated power control circuitry (PCC), which includes support for keyboard and mouse wake-up events.
The SCH5017 supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address, DMA Channel and hardware IRQ of each logical device in the SCH5017 may be reprogrammed through the internal configuration registers. There are up to 480 (960 - Parallel Port) I/O address location options, a Serialized IRQ interface, and Three DMA channels.
SCH5017 Data Sheet
