SED1374

Memory Interface
• Embedded 40K byte SRAM display buffer. CPU Interface
• Direct support of the following interfaces: Hitachi SH-3. Hitachi SH-4. Motorola M68K. MPU bus interface with programmable READY.
• Direct memory mapping of internal registers.
• CPU write buffer.
Display Support
• 4/8-bit monochrome LCD interface.
• 4/8-bit color LCD interface.
• 16-bit color LCD interface with minimal external curcuitry.
• Single-panel, single-drive passive displays.
• Dual-panel, dual-drive passive displays.
• Active Matrix TFT / TFD interface.
• Example resolutions: 640x480 at a color depth of 1 bpp 640x240 at a color depth of 2 bpp 320x240 at a color depth of 4 bpp 240x160 at a color depth of 8 bpp
Clock Source
• Single clock input for both pixel and memory clocks.
• The SED1374 clock source can be internally divided down for a higher frequency clock input.
• Dynamic switching of memory clocks in portrait mode.

The SED1374 is a color/monochrome LCD graphics controller with an embedded 40K Byte SRAM display buffer. The high integration of the SED1374 provides a low cost, low power, single chip solution to meet the requirements of embedded markets such as Office Automation equipment, Mobile Communications devices, and Hand-Held PCs where board size and battery life are major concerns.

Products requiring a "Portrait" display can take advantage of the Hardware Portrait Mode feature of the SED1374. Virtual and Split Screen are just some of the display modes supported. The above features, combined with the Operating System independence of the SED1374, make it the ideal solution for a wide variety of applications.