SG590

Features: · Supports Pentium®. Pentium® II & Pro CPUs.·Designed to meet Intel chipset specification· 12 CPU and 6 PCI clocks· One 48 MHz fixed clocks for USB.· One 24 MHz fixed clocks Super IO.· Separate power supply pins for mixed CPU, Fixed and PCI clock voltages· < 250 ps Max. sk...

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SG590 Picture
SeekIC No. : 004489154 Detail

SG590: Features: · Supports Pentium®. Pentium® II & Pro CPUs.·Designed to meet Intel chipset specification· 12 CPU and 6 PCI clocks· One 48 MHz fixed clocks for USB.· One 24 MHz fixed clocks Su...

floor Price/Ceiling Price

Part Number:
SG590
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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268 Transactions

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Upload time: 2025/12/25

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Product Details

Description



Features:

 · Supports Pentium®. Pentium® II & Pro CPUs.
 ·Designed to meet Intel chipset specification
 · 12 CPU and 6 PCI clocks
 · One 48 MHz fixed clocks for USB.
 · One 24 MHz fixed clocks Super IO.
 · Separate power supply pins for mixed CPU, Fixed and PCI clock voltages
 · < 250 ps Max. skew among CPU clocks.
 · < 250 ps Max. skew among PCI clocks.
 · Controlled current output buffers
 · 48-pin SSOP package
 · Spread Spectrum EMI reduction mode
 · Selectable Spread Widths
 



Pinout

  Connection Diagram


Specifications

Voltage Relative to VSS:.......................... -0.3V
Voltage Relative to VDD:........................... 0.3V
Storage Temperature:................ 0to + 125
Operating Temperature: ...............0 to +70
Maximum Power Supply:.............................. 5V

This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range:

                              VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).



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