SK100EP111

Features: • 100 ps Part-to-Part Skew• 35 ps Output-to-Output Skew• Differential Design• VBB Output• Low Voltage VEE Range of 2.375 to 3.8V for ECL• Low Voltage VCC Range of +2.375 to +3.8V for PECL and HSTL• 75 K Input Pulldown Resistors• ECL/PECL Ou...

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SK100EP111 Picture
SeekIC No. : 004491723 Detail

SK100EP111: Features: • 100 ps Part-to-Part Skew• 35 ps Output-to-Output Skew• Differential Design• VBB Output• Low Voltage VEE Range of 2.375 to 3.8V for ECL• Low Voltage VC...

floor Price/Ceiling Price

Part Number:
SK100EP111
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/25

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Product Details

Description



Features:

• 100 ps Part-to-Part Skew
• 35 ps Output-to-Output Skew
• Differential Design
• VBB Output
• Low Voltage VEE Range of 2.375 to 3.8V for ECL
• Low Voltage VCC Range of +2.375 to +3.8V for PECL and HSTL
• 75 K Input Pulldown Resistors
• ECL/PECL Outputs




Pinout

  Connection Diagram


Description

The SK100EP111 is a low skew 1-to-10 diffferential driver, designed with clock distribution in mind. SK100EP111 accepts two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended if the VBB output is used. HSTL inputs can be used when the EP111 is operating under PECL conditions. The selected signal is fanned out to 10 identical differential outputs.

The SK100EP111 is specifically designed, modeled, and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within a device, and characterization of SK100EP111 is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device.

To ensure that the tight skew specification is met, it is necessary that both sides of the differential output are terminated into 50W, even if only one side is being used. In most applications, all ten differential pairs of SK100EP111 will be used and therefore terminated. In the case where fewer than ten pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 1020 ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin.

The SK100EP111, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the EP111 to be used for high performance clock distribution in +3.3V or +2.5V systems. Designers of SK100EP111 can take advantage of the EP111's performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies.




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