SK10E142

The SK10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs of SK10E/100E142 do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.

The SEL (Select) input pin of SK10E/100E142 is used to switch between the two modes of operation SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers at set-up time before the posiitive going edge of CLK1 or CLK2. Shifting SK10E/100E142 is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero.