SK10E151

The SK10/100E151 offers 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new high-performance ECL systems. SK10/100E151 is fully compatible with MC10E151 and MC100E151. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for the flip-flops. Data is clocked into the flip-flops on the rising edge of either CLK1 or CLK2 (or both).

When both CLK1 and CLK2 of SK10/100E151 are at a logic LOW, data enters the master and is transferred to the slave when either CLK or CLK2 (or both) go HIGH. The MR (Master Reset) signal operates asynchronously to make all Q outputs go to a logic LOW.