SK10E445

The SK10/100E445 is an integrated 4-bit serial-toparallel data converter. The device is designed to operate for NRZ data rates of up to 2.0 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both 4-bit conversion and a two chip 8-bit conversion function. The conversion sequence was chosen to convert the first serial bit to Q0, the second to Q1, etc. Two selectable serial inputs provide a loopback capability for testing purposes when the SK10/100E445 is used in conjunction with the R446 parallel to serial converter.

The start bit for conversion can be moved using the SYNC input. A single pulse applied asynchronously for at least two input clock cycles shifts the start bit for conversion from Qn to Qn1. For each additional shift required, an additional pulse of SK10/100E445 must be applied to the SYNC input. Asserting the SYNC input will force the internal clock dividers to "swallow" a clock pulse, effectively shifting a bit from the Qn to the Qn1 output (see Timing Diagram B).

The MODE input is used to select the conversion mode of the device. With the MODE input LOW, or open, the SK10/100E445 will function as a 4-bit converter. When the mode input is driven HIGH, the data on the output will change on every eighth clock cycle, thus allowing for an 8-bit conversion scheme using two E445's. When cascaded in an 8-bit conversion scheme, the SK10/100E445 will not operate at the 2.0 Gb/s data rate of a single device. Refer to the applications section of this data sheet for more information on cascading the E445.

For lower data rate applications, a VBB reference voltage of SK10/100E445 is supplied for single-ended inputs. When operating at clock rates above 500 MHz, differential input signals are recommended. For single-ended inputs, the VBB pin is tied to the inverting differential input and bypassed via a 0.01 F capacitor. The VBB of SK10/100E445 provides the switching reference for the input differential amplifier. The VBB can also be used to AC couple an input signal.

Upon power-up, the internal flip-flops of SK10/100E445 will attain a random state. To synchronize multiple E445's in a system, the master reset must be asserted.