SK10LVE111E

The SK10/1000LVE111E is a low skew 1-to-9 differential driver designed with clock distribution in mind. The SK10/ 100LVE111EÕs function and performance are similar to the SK100E111, with the added feature of low voltage operation. It accepts one signal input which can be either differential or single-ended if the VBB output is used. The signal is fannedout to 9 identical differential outputs. An enable input is also  provided. A High disables the device by focing all Q outputs Low and all Q* outputs High.

The SK10/1000LVE111E is specifically designed, modeled, and produced with low skew as the key goal. Optimal design and layout serveto minimize gate-to-gate skew within a device, and  characterization of SK10/1000LVE111E is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device.

To ensure that the tight skew specification of SK10/1000LVE111E is met, it is necessarythat both sides of the differential output are terminated into 50W, even if only one side is being used. In most applications, all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs of SK10/1000LVE111E are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side in order to maintainminimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10Ð20ps)  October 6, 1928 Pin PLCC Package Preliminary Information This document contains information on a new product. The parametric
information, although not fully characterized, is the result of testing initial devices.

Low Voltage 1:9 Differential ECL / PECL Clock Driver of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin.

The SK10/100LVE111E, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. SK10/1000LVE111E allows the LVE111E to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE111EÕs performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For systems incorporating GTL, parallel termination of SK10/1000LVE111E offers the lowest power by taking advantage of the 1.2V supply as a terminating voltage.