SL4029B

Features: · Operating Voltage Range: 3.0 to 18 V· Maximum input current of 1 mA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C· Noise margin (over full package temperature range):-1.0 V min @ 5.0 V supply-2.0 V min @ 10.0 V supply-2.5 V min @ 15.0 V supplyPinoutSpecifications ...

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SL4029B Picture
SeekIC No. : 004492542 Detail

SL4029B: Features: · Operating Voltage Range: 3.0 to 18 V· Maximum input current of 1 mA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C· Noise margin (over full package temperature range...

floor Price/Ceiling Price

Part Number:
SL4029B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/25

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Product Details

Description



Features:

·  Operating Voltage Range: 3.0 to 18 V
·  Maximum input current of 1 mA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C
·  Noise margin (over full package temperature range):
-1.0 V min @ 5.0 V supply
-2.0 V min @ 10.0 V supply
-2.5 V min @ 15.0 V supply



Pinout

  Connection Diagram


Specifications

Symbol Parameter
Value
Unit
VCC DC Supply Voltage (Referenced to GND)
-0.5 to +20
V
VIN DC Input Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
VOUT DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
IIN DC Input Current, per Pin
±10
mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
PD Power Dissipation per Output Transistor
100
mW
Tstg Storage Temperature
-65 to +150
°C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
°C



Description

The SL4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consists of a single CLOCK, CARRY IN,(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs.

A high PRESET ENABLE signal of the SL4029B allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY IN and PRESET ENABLE signals are low. Advancement is inhibited when the CARRY IN orPRESET ENABLE signals are high. The CARRY OUT signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY IN signal is low. The CARRY IN signal in the low state can thus be considered a CLOCK ENABLE. TheCARRY IN terminal must be connected to GND when not in use.

Binary counting of the SL4029B is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low.

Parallel clocking provides synchronous control and hence faster of the SL4029B response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times.




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