Features: · Operating Voltage Range: 3.0 to 18 V· Maximum input current of 1 mA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C· Noise margin (over full package temperature range):-1.0 V min @ 5.0 V supply-2.0 V min @ 10.0 V supply-2.5 V min @ 15.0 V supplyPinoutSpecifications ...
SL4516B: Features: · Operating Voltage Range: 3.0 to 18 V· Maximum input current of 1 mA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C· Noise margin (over full package temperature range...
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| Symbol | Parameter |
Value |
Unit |
| VCC | DC Supply Voltage (Referenced to GND) |
-0.5 to +20 |
V |
| VIN | DC Input Voltage (Referenced to GND) |
-0.5 to VCC +0.5 |
V |
| VOUT | DC Output Voltage (Referenced to GND) |
-0.5 to VCC +0.5 |
V |
| IIN | DC Input Current, per Pin |
±10 |
mA |
| PD | Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ |
750 500 |
mW |
| PD | Power Dissipation per Output Transistor |
100 |
mW |
| Tstg | Storage Temperature |
-65 to +150 |
°C |
| TL | Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) |
260 |
°C |
The SL4516B Presettable Binary Up/Down Counter consists of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. This counter can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line.
If the CARRY-IN input of the SL4516B is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY-OUT of a less significant stage to the CARRYIN of a more significant stage.
The SL4516B can be cascaded in the ripple mode by connecting the CARRY-OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY-OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subsequent counting stage.