SL74HCT373

Features: ` TTL/NMOS-Compatible Input Levels` Outputs Directly Interface to CMOS, NMOS, and TTL` Operating Voltage Range: 4.5 to 5.5 V` Low Input Current: 1.0 APinoutSpecifications Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V ...

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SeekIC No. : 004492750 Detail

SL74HCT373: Features: ` TTL/NMOS-Compatible Input Levels` Outputs Directly Interface to CMOS, NMOS, and TTL` Operating Voltage Range: 4.5 to 5.5 V` Low Input Current: 1.0 APinoutSpecifications Symbol ...

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Part Number:
SL74HCT373
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/25

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Product Details

Description



Features:

`  TTL/NMOS-Compatible Input Levels
`  Outputs Directly Interface to CMOS, NMOS, and TTL
`  Operating Voltage Range: 4.5 to 5.5 V
`  Low Input Current: 1.0 A



Pinout

  Connection Diagram


Specifications

Symbol

Parameter

Value

Unit

VCC DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
VIN DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
VOUT DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
IIN DC Input Current, per Pin
±20
mA
IOUT DC Output Current, per Pin
±35
mA
ICC DC Supply Current, VCC and GND Pins
±75
mA
PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+
750
500
mW
Tstg Storage Temperature
-65 to +150
°C
TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
260
°C

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C




Description

The SL74HCT373 may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs.

The SL74HCT373 is identical in pinout to the LS/ALS373.

The eight latches of the SL74HCT373 are transparent D-type latches. While the Latch Enable is high the Q outputs follow the Data Inputs. When Latch Enable is taken low, data meeting the setup and hold times becomes latched.

The Output Enable of the SL74HCT373 does not affect the state of the latch, but when Output Enable is high, all outputs are forced to the high-impedance state. Thus, data may be latched even when the outputs are not enabled.




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