SM5819HQF

`512fs (22.5792MHz, fs = 44.1kHz), 1:2 to 2:1duty master clock
`DSD input and PCM output clock master/slaveswitching
`3-system external data input (3-wire format),PCM output data/BCK/LRCK external input andinternal filter output switching(BCK and LRCK are common to all 3 externalPCM data inputs)
`Decimation filter coefficients
• Fixed coefficients: 4fs-1/2fs-1/fs-1
`PCM output mute operation
`PCM output format: [MSB-first left-justified 32-bit] or [IIS 32-bit](IIS 32-bit output bit clock frequency = 64*wordclock frequency)
`FIR filter coefficients
• 64fs4fs/2fs/fs: 960th-order (6-channel)
• ROM coefficients: 24 valid data bits (4-bit MSBextension at 4fs, 5-bit MSB extension at 2fs/fs)
`+6dB DSD gain switching function
`External/Internal system clock output switching
`3.3V (3.0 to 3.6V) and 2.5V (2.3 to 2.7V) powersupplies
`−40 to 85°C operating temperature range
`48-pin QFP package